VHDL-FPGA-Verilog List Page 2650

VHDL-FPGA-Verilog list

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sdsdsd Downloaded：1: Cpu 8bit. Vorks good. Taking all instructions, sdo OR Xor and athor... Is registers
Date : 2025-11-22 Size : 8kb User : kaktusasturbo
Verilog Downloaded：0: Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
Date : 2025-11-22 Size : 317kb User : LEEY
turbo_encoder Downloaded：0: Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.
Date : 2025-11-22 Size : 24kb User : 黄一
new Downloaded：0: four bit shift register verilog code
Date : 2025-11-22 Size : 1kb User : aftab
shift_register Downloaded：0: It is noise generator.it is a linear feedback 16 shift-registe where the bits 15,14,12,3 are fed back via xor gates.make random signal close to real noise
Date : 2025-11-22 Size : 471kb User : sa
seven_segment Downloaded：0: It is seven segment decoder and display hexadecimal digits, and for wirting with vhdl use PACKAGE...
Date : 2025-11-22 Size : 331kb User : sa
memory Downloaded：0: DESIGN A SINGLE PORT MEMORY 8*256 using array with standard logic & tri_state gate, and simulate it by reading & writing word
Date : 2025-11-22 Size : 8.38mb User : sa
alu8bit Downloaded：0: it implement alu for 8 bit addition,subtraction,and ,or, left shift without overflow support and simulate it in modelsim
Date : 2025-11-22 Size : 400kb User : sa
FinitStateMashine Downloaded：0: implement finit state machine for finding "1010" pattern in a bit stream,there might be several after each other and also use one-hot state in modelsim
Date : 2025-11-22 Size : 373kb User : sa
shuzimiaobiao Downloaded：0: Stopwatch design block module design, the use of VHDL language
Date : 2025-11-22 Size : 75kb User : 林泽宇
16DIANTIKONGZHI Downloaded：0: 16 floors of elevator control program includes modules in VHDL program
Date : 2025-11-22 Size : 2kb User : 李灿
FPGA-and-DSP-based-on-the-Bayer-format-image-pre-p Downloaded：0: Real-time processing in the image process, the lower the amount of data preprocessing, simple operation, but requires high speed operation, you can use FPGA hardware processing, the data handled by upper layer less, comp
Date : 2025-11-22 Size : 95kb User : 汪江

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