VHDL-FPGA-Verilog List Page 2649

VHDL-FPGA-Verilog list

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VLSI Downloaded：0: CRC parallel 16-bit computing, is very powerful, very easy to use
Date : 2025-11-22 Size : 1.45mb User : zh
VerilogHDL Downloaded：0: Verilog HDL
Date : 2025-11-22 Size : 363kb User : 林海
counter Downloaded：0: commonly used VHDL modules, including counters, decoders, encoders, latches, etc., can be used as reference
Date : 2025-11-22 Size : 1kb User : nie
timer_led Downloaded：0: nios2 IDE, clock procedures to achieve its main function is as follows: 1. Displayed on the LCD screen time, date, status tips 2. On the console display time, date, status tips 3. Of the time, date to be set 4. In the ei
Date : 2025-11-22 Size : 3kb User : cd
Turbodecoders Downloaded：0: it consist of decoding of turbodecoders
Date : 2025-11-22 Size : 396kb User : manu
usb1.1 Downloaded：0: Verilog code for USB 1.1, has passed through the contents of the source code fpga
Date : 2025-11-22 Size : 62kb User : huipengliu
bookForEDA Downloaded：0: book form eda/vhdl
Date : 2025-11-22 Size : 216kb User : 李寡妇
SDRAM Downloaded：0: Introduced the principle of sdram, very detailed, you can reference for learners and developers
Date : 2025-11-22 Size : 1.85mb User : 萤火之光
74LS Downloaded：0: Digital Logic and System devices 74LS on the introduction of all the menu
Date : 2025-11-22 Size : 8.53mb User : 万淑红
code Downloaded：0: awet.etr.ert.ewtewjtr eqtr ert ert ewr erwrt ewrt ret5 asd er.
Date : 2025-11-22 Size : 1kb User : happybrave
CPLD-basedfrequencymeter Downloaded：0: CPLD-based multi-functional and so the design of precision digital frequency meter
Date : 2025-11-22 Size : 655kb User : 廖卫
CORDIC_FPGA Downloaded：0: Abstract: In this paper, based on the traditional CORDIC algorithm, by increasing the number of iterations, selection of parameters were optimized to improve the computing precision, the design of the soft-core to the oc
Date : 2025-11-22 Size : 223kb User : daisywmc

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