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UHF-RFID-CRC
Downloaded:0
The first,this paper investigates the f.0rward link and retum link data encodlng method in short range communication types A and B in ISO/IEC 1 8000-6,and deeply analyzes encoding method and technical parameters of Bi—Ph
Date
: 2025-11-22
Size
: 4.16mb
User
:
HY jian
LIP2908CORE_membist
Downloaded:1
Mem bist Verilog Module
Date
: 2025-11-22
Size
: 105kb
User
:
jc
LIP3001CORE_cpu
Downloaded:0
CPU Verilog Module source code
Date
: 2025-11-22
Size
: 159kb
User
:
jc
display
Downloaded:0
The objective of this lab is to understand and implement a simple character-based raster video display. As a result of completing this lab, you should have some appreciation for how a raster video display works. Your des
Date
: 2025-11-22
Size
: 1.47mb
User
:
liu
Arbitrary-points-frequency
Downloaded:0
Arbitrary points frequency
Date
: 2025-11-22
Size
: 26kb
User
:
liu
verilog-Division-calculation
Downloaded:0
verilog Division calculation
Date
: 2025-11-22
Size
: 249kb
User
:
liu
PS2-keyboard-controller-design
Downloaded:0
PS2 keyboard controller design
Date
: 2025-11-22
Size
: 851kb
User
:
liu
Simple-computer-design
Downloaded:0
Simple computer design and implementation
Date
: 2025-11-22
Size
: 155kb
User
:
liu
SATA_Verification_IP-SystemVerilog
Downloaded:0
SATA Verification IP- SystemVerilog, is to use FPGA to do sata interface part, is a document
Date
: 2025-11-22
Size
: 394kb
User
:
磊
sdram_sv
Downloaded:0
sdram VerilogHDL under the quartus description is accurate SystemVerilog, has been commissioning successful, but not using burst transmission, the simulation file containing modulesim.
Date
: 2025-11-22
Size
: 4.72mb
User
:
Anthony
FPGA-VHDL-dengjingduc
Downloaded:0
This article describes the decimal-based VHDL, and other precision frequency meter design, using VHDL language, the use of top-down design, the system is divided by function layer hierarchical design method, the use of Q
Date
: 2025-11-22
Size
: 274kb
User
:
筱诺
source
Downloaded:0
Copy-bit
Date
: 2025-11-22
Size
: 5kb
User
:
李拉
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