VHDL-FPGA-Verilog List Page 2582

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .77 .78 .79 .80 .81 2582.83 .84 .85 .86 .87 ... 4310 »

Circuit-modeling-mux Downloaded：0: Circuit modeling- simple and complex signals Mux modeling thought, expression, etc.
Date : 2025-11-22 Size : 28kb User : 李拉
dmx512 Downloaded：0: C source code of the receiving program DMX512, DMX512 receiving program
Date : 2025-11-22 Size : 1kb User : itsemi
Shannon-expansion-of-Boolean-logic Downloaded：0: Shannon expansion of Boolean logic or extension, is simply the reverse Carnot logical operations. Shannon expansion is equivalent to the logical replication, increased frequency and simplification of the equivalent Carno
Date : 2025-11-22 Size : 41kb User : 李拉
clock-synchronized-registers Downloaded：0: In general, CPU clock will read and write the introduction to the PLD, the author uses the CPU to read and write clock synchronized read and write registers, improve design reliability. This modeling approach is therefor
Date : 2025-11-22 Size : 88kb User : 李拉
delay Downloaded：0: 1. Blocking_LHS_Delay: blocking assignment left-style delay. 2. Blocking_RHS_Delay: blocking assignment the right-style delay. 3. NonBlocking_LHS_Delay: non-blocking assignment left-style delay. 4. NonBlocking_RHS_Delay:
Date : 2025-11-22 Size : 7kb User : 李拉
Testbench Downloaded：0: Testbench to know more structured way to the top
Date : 2025-11-22 Size : 151kb User : 李拉
PIC-SPI Downloaded：0: PIC16F877A for SPI communication, the data sent to the 25C040, also shows the data read out from the 25C040
Date : 2025-11-22 Size : 19kb User : lyhas
Schmitt-trigger-keyboard-interface Downloaded：0: Schmitt trigger on the keyboard interface circuit, effectively reducing the trigger delay and shorten the reaction time to verilog implementation keyboard
Date : 2025-11-22 Size : 1.05mb User : 李拉
digicnt1 Downloaded：0: 24 hours of positive and negative timer. Achieved through two key zero, and positive and negative time, with a pause and resume button. 48MHz crystal, 7 segment LED output.
Date : 2025-11-22 Size : 487kb User : 夏江南
Verilog Downloaded：0: There are two types in the Verilog assignment statement: continuous assignment and process assignment. Assignment expression consists of three parts: the left value, the assignment operator (= or < =) and the right val
Date : 2025-11-22 Size : 5kb User : 林林
digital-system-design Downloaded：0: SEVEN SEGMENT DISPLAY
Date : 2025-11-22 Size : 172kb User : 周兴业
USB2.0-IP-core Downloaded：0: Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help
Date : 2025-11-22 Size : 196kb User : 柳同学

« 1 2 ... .77 .78 .79 .80 .81 2582.83 .84 .85 .86 .87 ... 4310 »

Search in result