There are two types in the Verilog assignment statement: continuous assignment and process assignment. Assignment expression consists of three parts: the left value, the assignment operator (= or < =) and the right values. Right values can be any type of data, including net type and register type but continuous assignment, the left value must be a net type of data the process of assignment, the left value must be a register type of data. Described in detail below

Verilog.doc

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