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VHDL-FPGA-Verilog list
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simple demultiplexer on 4 bits
Date : 2025-11-23 Size : 3kb User : vlad

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d flip flop for demonstration purposes
Date : 2025-11-23 Size : 3kb User : vlad

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Experimental design of a CPU, designed a very simple CPU
Date : 2025-11-23 Size : 106kb User : 张国玉

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adder verilog language design synchronous, asynchronous subtractor, 16-bit counter
Date : 2025-11-23 Size : 745kb User : 白叶叶

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32-byte by 8-bit verilog RAM (triggers and M4K), achieved by LPM RAM
Date : 2025-11-23 Size : 254kb User : 白叶叶

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verilog to achieve traffic control lights, can show the direction of crossing the state, the countdown to red, yellow, green and can generally be cleared
Date : 2025-11-23 Size : 7.49mb User : 白叶叶

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Seven-Segment LED
Date : 2025-11-23 Size : 1.25mb User : 占雪妍

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The design is based on FPGA technology, used to generate a certain frequency width of the sine wave, square wave and rectangular wave
Date : 2025-11-23 Size : 1kb User : 杨雪

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System uses the accelerometer as the input signal, after analog-digital conversion and enter the FPGA development platform, to achieve the balance shown on the display the ball game. Procedures have been compiled, a comp
Date : 2025-11-23 Size : 10.5mb User :

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sf dfs
Date : 2025-11-23 Size : 286kb User : 王雪华

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vhdl of sound and implemnt it
Date : 2025-11-23 Size : 157kb User : elishba

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Digital filter design and FPGA realization of forming this paper, the digital baseband signal pulse shaping filter applications, principle and implementation were studied.
Date : 2025-11-23 Size : 642kb User : rei
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