VHDL-FPGA-Verilog List Page 2396

VHDL-FPGA-Verilog list

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abc Downloaded：1: Convolutional code encoder implementation, using vhdl language. This is done when the complete set has been transferred through.
Date : 2025-11-23 Size : 4kb User : decoder
FK Downloaded：0: Decimal counter counting to achieve continuous, control, LED display ten numbers 0-9
Date : 2025-11-23 Size : 112kb User : ziying
example Downloaded：0: This is a FPGA-based controller design is based on a variety of air-conditioning function of the basic
Date : 2025-11-23 Size : 1kb User : 黄石
seccount Downloaded：0: With VHDL language design digital stopwatch. Contains the corresponding code and all documents. Users can Xilinx ISE environment in operation
Date : 2025-11-23 Size : 647kb User : chenlan
fir Downloaded：0: With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
Date : 2025-11-23 Size : 459kb User : chenlan
multiplier_ip Downloaded：0: Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
Date : 2025-11-23 Size : 2.66mb User : chenlan
multiply_shift_add Downloaded：0: Adding operation based on shift on time-multiplier design, multiply_shift_add contains the complete design engineering documents, Xilinx ISE in running
Date : 2025-11-23 Size : 1.02mb User : chenlan
pwm Downloaded：0: With a dead zone, the frequency can be set in the PWM output source, have been applied in practice
Date : 2025-11-23 Size : 1kb User : xuning
smc Downloaded：0: Clock countdown, countdown function can be well implemented, has been verified, a good reference work for beginners
Date : 2025-11-23 Size : 527kb User : xuning
8237a Downloaded：0: simple dma controller in vhdl
Date : 2025-11-23 Size : 4kb User : dyded
2011-EDA-1 Downloaded：0: EDA-Electronic Innovate Design
Date : 2025-11-23 Size : 455kb User : zhoucl
DMA-CORE Downloaded：0: simple verilog dma source
Date : 2025-11-23 Size : 7kb User : dyded

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