VHDL-FPGA-Verilog List Page 2391

VHDL-FPGA-Verilog list

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dfghg Downloaded：0: With synchronous reset the state machine! State machine can be used to understand the principles of programming and formats, as well as the realization of synchronous reset!
Date : 2025-11-23 Size : 1kb User : funny
Libero_UG Downloaded：0: libero use of detailed tutorials, a more detailed tutorial than the official website for more details
Date : 2025-11-23 Size : 11.75mb User : funny
UART Downloaded：0: VHDL language programming with UART, 8 data bits, parity bit that they can add! LIBERO simulation correctly!
Date : 2025-11-23 Size : 14kb User : funny
uart_flash Downloaded：0: UART control of flash to achieve
Date : 2025-11-23 Size : 1.95mb User : wang
dsp_test Downloaded：0: FPGA implementation using floating-point DSP, VHDL code
Date : 2025-11-23 Size : 3.08mb User : wang
eda Downloaded：0: The system uses VHDL language, PLD design taxi billing system to MAX+ PLUS Ⅱ software as a development platform, the taxi meter system was designed and conducted a program simulation program. To achieve automotive billin
Date : 2025-11-23 Size : 161kb User : OFDM
modelsim_guide_cn Downloaded：0: Design simulation using ModelSim HDL simulator ModelSim is, we can use the software to achieve the program designed to simulate VHDL or Verilog, to support a variety of common IEEE standard hardware description language.
Date : 2025-11-23 Size : 334kb User : 谢明
in-ModelSim-and-Xilinx-lib Downloaded：0: ModelSim SE configured in the library function in Modelsim Xilinx installation root directory create a new folder to put all the library files xilinx, it can be named xilinx_lib. Similar Xinlinx installation file: \ .. \
Date : 2025-11-23 Size : 104kb User : 谢明
ADS2807ctrl Downloaded：0: ADS2807 control FPGA board using TI' s ADS2807 high-speed AD chip analog signal acquisition, the maximum speed of up to 50MPS, must be controlled by FPGA. Timing diagram of its work as follows:
Date : 2025-11-23 Size : 466kb User : 谢明
CRC10 Downloaded：0: CRC check
Date : 2025-11-23 Size : 1kb User : wenxin
Addr_Generator Downloaded：0: Where start is the start signal, the rising edge of start control unit CLK is a working clock CtrlAddr is to read the control word address CtrlData is to read the control word Reading is a reading of the signal EOP is a
Date : 2025-11-23 Size : 1kb User : 谢明
uart Downloaded：0: System on a chip design examples and source code analysis UART
Date : 2025-11-23 Size : 9kb User : 谢伟峰

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