VHDL-FPGA-Verilog List Page 2315

VHDL-FPGA-Verilog list

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cordic_verilogfiles Downloaded：0: Design of FFT on FPGA using VHDL
Date : 2025-11-23 Size : 803kb User : joseph
chengxu Downloaded：0: EDA experimental procedures to achieve 8-bit full adder, counter 999 and frequency counter digital display shows the source. . . To be tested.
Date : 2025-11-23 Size : 472kb User : 刘文涛
Roth---Digital-system-design-with-VHDL.-1998.pdf. Downloaded：0: Digital Systems Design Using VHDL
Date : 2025-11-23 Size : 5.23mb User : gamlet
conter Downloaded：0: code of a counter with vhdl very hey description language it counts from 0 to 255
Date : 2025-11-23 Size : 1kb User : med
videocomposer Downloaded：0: video composer in vhdl
Date : 2025-11-23 Size : 6kb User : ankita
huaqiaodaxue_NIOS_DEVICE_LED Downloaded：0: Chinese University of dedicated experimental program code to achieve led testing. Huaqiao University eda laboratory dedicated
Date : 2025-11-23 Size : 3.78mb User : twieain
huaqiaodaxue--DE2_NET Downloaded：0: Chinese University of dedicated experimental program code, data packets sent over the network to achieve de2, Huaqiao University laboratory. Huaqiao University eda laboratory dedicated
Date : 2025-11-23 Size : 1.53mb User : twieain
huaqiaodaxue---DE2_SD_Card_Audio Downloaded：0: Chinese University of dedicated experimental program code to achieve sdram play music. Huaqiao University eda laboratory dedicated
Date : 2025-11-23 Size : 1.53mb User : twieain
huaqiaodaxue_NIOS_HOST_MOUSE_VGA Downloaded：0: Chinese University of dedicated experimental program code to realize the control of a computer mouse. Huaqiao University eda laboratory dedicated
Date : 2025-11-23 Size : 1.55mb User : twieain
red-and-green Downloaded：0: Traffic light code, when the green light under the two measured cross-road traffic, more traffic lights to change the size of the time immediately after the maximum change in 20 seconds.
Date : 2025-11-23 Size : 1kb User : lily
testspeed Downloaded：0: Transformation process in real time the traffic lights, after receiving the signal for the road traffic statistics, a high level representative of a car. And is able to compare the two road traffic calculation value base
Date : 2025-11-23 Size : 1kb User : lily
clkdivverilog Downloaded：0: Verilog program the clock frequency of entry based on experimental privileged students EPM240
Date : 2025-11-23 Size : 156kb User : kevin

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