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VHDL-FPGA-Verilog list
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jiaotongdeng
Downloaded:0
Has two access channels, respectively, along the direction 1 and direction 2 to pass. Each direction has a red, yellow, green, composed of traffic lights. The signal from the corresponding high signal (R1, G1, Y1, R2, G2
Date
: 2025-11-23
Size
: 40kb
User
:
xyl
Part1
Downloaded:0
Quartus Lab 1 Part 1 solution for the DE2 development board
Date
: 2025-11-23
Size
: 316kb
User
:
gazzaman
60and24
Downloaded:0
A 60 and 24 hex vhdl example (tested easy to use)
Date
: 2025-11-23
Size
: 229kb
User
:
李辉
vote7_plus
Downloaded:0
Seven voting integrity project, VHDL language, Maxplus2 environment, there are simulation diagram, experimental available ~ ~
Date
: 2025-11-23
Size
: 412kb
User
:
Andrew
i28f128p30
Downloaded:0
Intel Strata Flash Memory (P30) interface controller of the VHDL source code
Date
: 2025-11-23
Size
: 18kb
User
:
wangyu
5421bcd
Downloaded:0
5421bcd vhdl
Date
: 2025-11-23
Size
: 404kb
User
:
刘文
leon
Downloaded:0
LEON processors, open source. Can be configured to download to the FPGA. An open source processor. Wide range of aerospace applications.
Date
: 2025-11-23
Size
: 21.21mb
User
:
haibo
weideng
Downloaded:0
With the VHDL language to describe the car in traffic, turn left, turn right, driving the rear brake and normal control state
Date
: 2025-11-23
Size
: 113kb
User
:
晴峦
final
Downloaded:0
This Source is Verilog Coding. Made in Altera Quartus 9.0 Service Pack 3. Important, I know not used board.
Date
: 2025-11-23
Size
: 129kb
User
:
SongJiYoon
CRC
Downloaded:0
26 bits of the frame structure of 6-bit CRC processing, output 26+6 = 32 frame structure. VHDL code
Date
: 2025-11-23
Size
: 1kb
User
:
杨胜丰
INTERLEAVER
Downloaded:0
1/3, k = 9 convolutional code VHDL implementation of the simulation in the xilinx ise success.
Date
: 2025-11-23
Size
: 1kb
User
:
杨胜丰
netAD0809
Downloaded:0
verilog description of AD
Date
: 2025-11-23
Size
: 1kb
User
:
李渊
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.09
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2313
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.17
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4310
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