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VHDL-FPGA-Verilog list
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SSD1289_16BIT_GUI
Downloaded:0
SSD1289 codes ive wrote, v obshti linii pisha toq bul0-6it, za da drupna drug bul
Date
: 2025-11-24
Size
: 7kb
User
:
boiko
shudianshiyan
Downloaded:0
Digital circuits and logic design experiments programming, including multi-function electronic clock procedures, practical, simple
Date
: 2025-11-24
Size
: 3.21mb
User
:
sunnxbest
caideng-xulie
Downloaded:0
Digital circuits and logic programming design experiments, and experiments with lights experiments sort sequence.
Date
: 2025-11-24
Size
: 333kb
User
:
sunnxbest
wf1
Downloaded:0
dds signal generator, signal generator based on fpga, with basic functions,
Date
: 2025-11-24
Size
: 2.56mb
User
:
尼加提
ddr_sdr
Downloaded:0
DDR SDRAM control
Date
: 2025-11-24
Size
: 113kb
User
:
李晓翔
uart_tx_2
Downloaded:0
VHDL Code for UART Transmitter
Date
: 2025-11-24
Size
: 1kb
User
:
hani
e4
Downloaded:0
left-right shifter
Date
: 2025-11-24
Size
: 4kb
User
:
蚂蚁
dds_vhdl
Downloaded:0
DDS Program Description module containing the port settings and random access memory design
Date
: 2025-11-24
Size
: 1kb
User
:
打算法
dds1
Downloaded:0
DDS design of the original program, sub-file contains the adder, flip-flops, RAM, and other modules designed to achieve a simple simulation
Date
: 2025-11-24
Size
: 565kb
User
:
打算法
RS232
Downloaded:0
RS232 IS USED FOR DATA TRANSFER..RS STANDS FOR RECOMMENDED STANDARD
Date
: 2025-11-24
Size
: 826kb
User
:
sandeep
vga
Downloaded:0
FPGA-based VGA timing generator/controller, resulting in horizontal and vertical sync timing, and a standard format output, and the corresponding test code. Development tool ISE 8.1 and above.
Date
: 2025-11-24
Size
: 126kb
User
:
微尘
Multifunction_Digital_Clock
Downloaded:0
Achieve multi-functional digital clock in the spartan-3E development board development.
Date
: 2025-11-24
Size
: 1.51mb
User
:
kimoo
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.28
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2233
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.35
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.37
.38
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