Digital circuits and logic design experiments programming, including multi-function electronic clock procedures, practical, simple

数电实验\AM.vhd
........\change.vhd
........\changetime.vhd
........\change_2.vhd
........\clock.vhd
........\couter10.vhd
........\couter6.vhd
........\div_1M.vhd
........\div_5k.vhd
........\modechange.vhd
........\seg7_1.vhd
........\show.vhd
........\shujuxuanzeqi.vhd
........\twentyfourhour.vhd
........\数字逻辑实验.doc
数电实验
........\1\AM.vhd
........\.\change.vhd
........\.\changetime.vhd
........\.\change_2.vhd
........\.\clock.vhd
........\.\couter10.vhd
........\.\couter6.vhd
........\.\div_1M.vhd
........\.\div_5k.vhd
........\.\modechange.vhd
........\.\seg7_1.vhd
........\.\show.vhd
........\.\shujuxuanzeqi.vhd
........\.\twentyfourhour.vhd
........\.\数字逻辑实验.doc
........\2\10\addtime.vhd
........\.\..\clock.asm.rpt
........\.\..\clock.done
........\.\..\clock.dpf
........\.\..\clock.fit.rpt
........\.\..\clock.fit.summary
........\.\..\clock.flow.rpt
........\.\..\clock.map.rpt
........\.\..\clock.map.summary
........\.\..\clock.pin
........\.\..\clock.pof
........\.\..\clock.qpf
........\.\..\clock.qsf
........\.\..\clock.qws
........\.\..\clock.tan.rpt
........\.\..\clock.tan.summary
........\.\..\clock.vhd
........\.\..\clock.vhd.bak
........\.\..\convert_to_ten.vhd
........\.\..\counter12.vhd
........\.\..\counter24.vhd
........\.\..\counter60.vhd
........\.\..\counter60.vhd.bak
........\.\..\counter60_fen.vhd
........\.\..\counter60_miao.vhd
........\.\..\db\abs_divider_bag.tdf
........\.\..\..\add_sub_6ph.tdf
........\.\..\..\add_sub_7kh.tdf
........\.\..\..\add_sub_dph.tdf
........\.\..\..\add_sub_h1f.tdf
........\.\..\..\add_sub_k1f.tdf
........\.\..\..\add_sub_m9c.tdf
........\.\..\..\add_sub_n9c.tdf
........\.\..\..\add_sub_o4c.tdf
........\.\..\..\add_sub_o9c.tdf
........\.\..\..\add_sub_p9c.tdf
........\.\..\..\add_sub_pnh.tdf
........\.\..\..\add_sub_q9c.tdf
........\.\..\..\add_sub_r4c.tdf
........\.\..\..\add_sub_r9c.tdf
........\.\..\..\alt_u_div_tke.tdf
........\.\..\..\alt_u_div_vke.tdf
........\.\..\..\clock.asm.qmsg
........\.\..\..\clock.cbx.xml
........\.\..\..\clock.cmp.cdb
........\.\..\..\clock.cmp.hdb
........\.\..\..\clock.cmp.logdb
........\.\..\..\clock.cmp.rdb
........\.\..\..\clock.cmp.tdb
........\.\..\..\clock.cmp0.ddb
........\.\..\..\clock.db_info
........\.\..\..\clock.eco.cdb
........\.\..\..\clock.fit.qmsg
........\.\..\..\clock.hier_info
........\.\..\..\clock.hif
........\.\..\..\clock.map.cdb
........\.\..\..\clock.map.hdb
........\.\..\..\clock.map.logdb
........\.\..\..\clock.map.qmsg
........\.\..\..\clock.pre_map.cdb
........\.\..\..\clock.pre_map.hdb
........\.\..\..\clock.rtlv.hdb
........\.\..\..\clock.rtlv_sg.cdb
........\.\..\..\clock.rtlv_sg_swap.cdb
........\.\..\..\clock.sgdiff.cdb
........\.\..\..\clock.sgdiff.hdb
........\.\..\..\clock.sld_design_entry.sci
........\.\..\..\clock.sld_design_entry_dsc.sci
........\.\..\..\clock.syn_hier_info

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