VHDL-FPGA-Verilog List Page 2232

VHDL-FPGA-Verilog list

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ModelSim__Video1 Downloaded：0: Chinese version of Modelsim simulation video tutorial, detailed
Date : 2025-11-24 Size : 18.9mb User : 微尘
asic_study Downloaded：0: ASCI is compressed package learning materials, including a laboratory in Taiwan Sun Yat-ASIC synthesis scripts tutorials, National Chiao Tung University, published a springer to do household system verilog verification b
Date : 2025-11-24 Size : 2.52mb User : xueer
e011_timingdesigner Downloaded：0: FPGA design timing necessary software. Logic design can effectively improve the speed of adjustment of the design timing.
Date : 2025-11-24 Size : 29.68mb User : xueer
GNSS Downloaded：0: With altium designer painting DSP+ FPGA+ USB2.0 schematic diagram of the system
Date : 2025-11-24 Size : 414kb User : ly19900119
ook Downloaded：0: OOK generated random code, can be used to QuartusII of the ROM or RAM.
Date : 2025-11-24 Size : 2kb User : ye
FPGA--multi_clock-system-design Downloaded：0: China University of Science and technology multi_clock system design
Date : 2025-11-24 Size : 312kb User : ye
DA-FIR-FPGA Downloaded：0: Detailed design of a distributed algorithm FIR, FPGA implementation for the FIR design with a guide. From HUST.
Date : 2025-11-24 Size : 284kb User : ye
d_e_g_dds Downloaded：0: Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. From HUST.
Date : 2025-11-24 Size : 1.2mb User : ye
OFDM_retiming Downloaded：0: Verilog-OFDM-based clock recovery module, doing all-digital OFDM time is the key module can be implemented on the FPGA.
Date : 2025-11-24 Size : 170kb User : ye
pc_cfr_test_v3_1c Downloaded：0: A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect!
Date : 2025-11-24 Size : 3kb User : baomeng
EDA Downloaded：0: This an introductory book EDA technology, mainly about the VHDL hardware description language in the digital electronic system design application, informative and easy to understand, contribute to learning VHDL.
Date : 2025-11-24 Size : 836kb User : 元泽怀
DAC0832-VHDL-design Downloaded：0: DAC0832 interface VHDL design and implementation. Using hardware description language DAC function in the FPGA.
Date : 2025-11-24 Size : 3kb User : 元泽怀

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