FPGA-based VGA timing generator/controller, resulting in horizontal and vertical sync timing, and a standard format output, and the corresponding test code. Development tool ISE 8.1 and above.

vga\automake.log
...\coregen.log
...\coregen.prj
...\generic_dpram.v
...\generic_spram.v
...\prjname.lso
...\sync_check.v
...\tests.v
...\tests.v.bak
...\test_bench_top.v
...\test_bench_top.v.bak
...\timescale.v
...\vga.dhp
...\vga.npl
...\vga_clkgen.v
...\vga_colproc.v
...\vga_csm_pb.v
...\vga_curproc.v
...\vga_cur_cregs.v
...\vga_defines.v
...\vga_defines.v.bak
...\vga_enh_top.cmd_log
...\vga_enh_top.lso
...\vga_enh_top.prj
...\vga_enh_top.stx
...\vga_enh_top.syr
...\vga_enh_top.v
...\vga_enh_top_vhdl.prj
...\vga_fifo.v
...\vga_fifo_dc.v
...\vga_pgen.v
...\vga_tgen.v
...\vga_vtim.v
...\vga_wb_master.v
...\vga_wb_master.v.bak
...\vga_wb_slave.v
...\vga_wb_slave.v.bak
...\wb_b3_check.v
...\wb_b3_check.v.bak
...\wb_mast_model.v
...\wb_model_defines.v
...\wb_model_defines.v.bak
...\wb_slv_model.v
...\wb_slv_model.v.bak
...\__projnav.log
...\.........\coregen.rsp
...\.........\runXst_tcl.rsp
...\.........\vga.gfl
...\.........\vga_enh_top.xst
...\.........\vga_flowplus.gfl
...\.........\xst_sprjTOstx_tcl.rsp
...\xst\work\hdllib.ref
...\...\....\vlg7B\vga_tgen.bin
...\...\....\...6A\vga_enh_top.bin
...\...\....\...5F\vga_colproc.bin
...\...\....\....D\vga_fifo.bin
...\...\....\....9\vga_clkgen.bin
...\...\....\....3\generic_spram.bin
...\...\....\...4D\vga_csm_pb.bin
...\...\....\.....\vga_vtim.bin
...\...\....\...34\generic_dpram.bin
...\...\....\...07\vga_fifo_dc.bin
...\...\....\.....\vga_pgen.bin
...\...\....\....5\vga_wb_master.bin
...\...\....\....4\vga_wb_slave.bin
...\...\....\vlg7B
...\...\....\vlg6A
...\...\....\vlg5F
...\...\....\vlg5D
...\...\....\vlg59
...\...\....\vlg53
...\...\....\vlg4D
...\...\....\vlg34
...\...\....\vlg07
...\...\....\vlg05
...\...\....\vlg04
...\...\work
...\__projnav
...\xst
vga

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