VHDL-FPGA-Verilog List Page 2012

VHDL-FPGA-Verilog list

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rs232_syscon_latest.tar Downloaded：0: After serial communication process, can be received, the data processing, source opencore
Date : 2025-09-19 Size : 551kb User : asfk
buffered-cpu-interfact.tar Downloaded：0: This is a fully synchronous (single clock domain, no asynchronous resets) UART with a FIFO buffered cpu interfact
Date : 2025-09-19 Size : 8kb User : asfk
EasyFPGA030- Downloaded：0: With EasyFPGA030 development board to implement serial communication interface, through the computer sends the appropriate data, the control panel LED lamp and a specific port-level changes.
Date : 2025-09-19 Size : 236kb User : asfk
MCU Downloaded：0: Including two-way communication with the MCU, counters, registers, etc., yourself, can be used after the class is absolutely H-bridge. Is a brushed DC motor
Date : 2025-09-19 Size : 1.06mb User : asfk
111 Downloaded：0: A complete SDRAM debugger, run in QuartusII ensure available.
Date : 2025-09-19 Size : 2.75mb User : 胡飞
de- Downloaded：0: Arbitrary waveform generator, hand-painted, photo+ paper (containing part of the source) source ourdev
Date : 2025-09-19 Size : 901kb User : asfk
Traffic_lights Downloaded：0: With VerilogHDL programming, software simulation in QuartusII traffic lights to achieve a simple procedure.
Date : 2025-09-19 Size : 1kb User : LT
EDAandVerilog-HDL Downloaded：0: This an EDA technology and Verilog language books, great for the EDA to help learners
Date : 2025-09-19 Size : 26.77mb User : hanwang
SDRAMPNIOS-II Downloaded：0: With the nios II SDRAM system, development environment for the Quartus II 9.0+ Nios II 9.0
Date : 2025-09-19 Size : 7.05mb User : 张非
PoE_2temac_TOP Downloaded：0: 1000Mhz Ethernet TEMAC xilinx fpga vhdl RTL
Date : 2025-09-19 Size : 1kb User : fan.r
HW Downloaded：0: DE1 demo code
Date : 2025-09-19 Size : 595kb User : wangting
vote7 Downloaded：0: Achieve seven votes, more than four people voted, or not through
Date : 2025-09-19 Size : 1kb User : 闫

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