With EasyFPGA030 development board to implement serial communication interface, through the computer sends the appropriate data, the control panel LED lamp and a specific port-level changes.

asyn\asyn.prj
....\designer\impl1\async.adb
....\........\.....\......dtf\verify.log
....\........\.....\async.ide_des
....\........\.....\async.pdb
....\........\.....\async.pdb.depends
....\........\.....\async.tcl
....\........\.....\....._fp\$$FlashPro_FPBBALTLPT1.L$$
....\........\.....\........\async.log
....\........\.....\........\async.pro
....\........\.....\........\projectData\async.pdb
....\........\.....\async_receiver.ide_des
....\........\.....\async_transmitter.ide_des
....\........\.....\designer.log
....\hdl\async.v
....\...\async_receiver.v
....\...\async_transmitter.v
....\simulation\modelsim.ini
....\.martgen\smartgen.aws
....\.ynthesis\.recordref
....\.........\async.areasrr
....\.........\async.edn
....\.........\async.map
....\.........\async.pdc
....\.........\async.sdf
....\.........\async.so
....\.........\async.srd
....\.........\async.srm
....\.........\async.srr
....\.........\async.srs
....\.........\async.szr
....\.........\async.tlg
....\.........\async_sdc.sdc
....\.........\async_syn.prj
....\.........\run_options.txt
....\.........\stdout.log
....\.........\.yntmp\async.plg
....\.........\traplog.tlg
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\designer\impl1\async_fp\projectData
....\........\.....\async.dtf
....\........\.....\async_fp
....\........\.....\simulation
....\........\impl1
....\synthesis\backup
....\.........\coreip
....\.........\syntmp
....\viewdraw\sch
....\........\sym
....\........\vf
....\........\wir
....\component
....\constraint
....\coreconsole
....\designer
....\hdl
....\phy_synthesis
....\simulation
....\smartgen
....\stimulus
....\synthesis
....\viewdraw
asyn

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