VHDL-FPGA-Verilog List Page 2011

VHDL-FPGA-Verilog list

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« 1 2 ... .06 .07 .08 .09 .10 2011.12 .13 .14 .15 .16 ... 4310 »

DE1_i2sound Downloaded：0: DE1 development board case, the development board with the code DE1_i2sound.rar
Date : 2025-09-19 Size : 2.06mb User : wangting
DE1_Default Downloaded：0: DE1 development board case, the development board with the code 3 DE1_Default.rar
Date : 2025-09-19 Size : 429kb User : wangting
DE1_NIOS Downloaded：0: DE1 development board case, based on the use of DE1_NIOS.rar NIOS
Date : 2025-09-19 Size : 10.38mb User : wangting
DE1_SD_Card_Audio Downloaded：0: DE1 development board project development case, DE1_SD_Card_Audio
Date : 2025-09-19 Size : 12.84mb User : wangting
vga Downloaded：0: vga display program, vhdl, can display a picture on vga monitor
Date : 2025-09-19 Size : 3.32mb User : 李亮
jiaotongdeng Downloaded：0: jiao tongdeng
Date : 2025-09-19 Size : 24kb User : name
single_cpu Downloaded：0: Single-cycle CPU in Verilog developed on XilinxISE 10.1
Date : 2025-09-19 Size : 3.05mb User : Vincent
FPGADesign Downloaded：0: Huawei hardware engineers FPGA design specifications, including the two languages
Date : 2025-09-19 Size : 1.95mb User : xiaojf
fir4 Downloaded：0: Based on the length of 4 vhdl fir filter, after the official software certification
Date : 2025-09-19 Size : 1kb User : 李亮
seg7 Downloaded：0: Four seven-segment LED display scanning circuit, the use of 50mhz frequency input frequency into the scan frequency, and then display four digits
Date : 2025-09-19 Size : 1kb User : 陈淑靖
alu-10-10 Downloaded：0: 16-bit arithmetic unit, including+,-, and or, shift and other functions, within the specified a, b, cin, input clk and rst, 16-bit output y and c \ z flag
Date : 2025-09-19 Size : 2kb User : 张海洋
irda_rx Downloaded：0: Infrared transceiver receiver module, very very strong. Using Verilog design and simulation using Modelsim, function entirely correct.
Date : 2025-09-19 Size : 4.51mb User : iswl2009

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