VHDL-FPGA-Verilog List Page 1961

VHDL-FPGA-Verilog list

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timer Downloaded：0: something about timer
Date : 2025-09-19 Size : 11.13mb User : hq
Altera.FPGA Downloaded：0: something about fpga
Date : 2025-09-19 Size : 24.62mb User : hq
generic_fifo_yh Downloaded：0: Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portabl
Date : 2025-09-19 Size : 37kb User : 杨豪
PL_FSK Downloaded：0: FSK modulation
Date : 2025-09-19 Size : 157kb User : 朱捷
taxi_1 Downloaded：0: Taxi meter time sequence emulation
Date : 2025-09-19 Size : 164kb User : 朱捷
CCD285_DRIVER_11927 Downloaded：0: a ccd driver code,wirte in verilog,there are some error in the timing analyzer in the report after full compiled ,but the wafes on oscillograph are successful
Date : 2025-09-19 Size : 2kb User : jldeng
clock_1Hz Downloaded：1: Clock 1Hz with duty cycle control for verilog for DE2-115 Altera FPGA
Date : 2025-09-19 Size : 7.61mb User : luis
Monitor_LRRV Downloaded：0: Quick test to handle VGA monitor enabling four colors on screen, Verilog Code Source using internal 50MHz clock signal.
Date : 2025-09-19 Size : 2.03mb User : luis
comparator_4bit Downloaded：0: Basic 4-bit Comparator project in verilog
Date : 2025-09-19 Size : 2.86mb User : luis
decoder_bcd7seg Downloaded：0: Basic 7-segment decoder for Verilog
Date : 2025-09-19 Size : 2.89mb User : luis
ones_counter Downloaded：0: Ones counter for Verilog, basic project for Altera FPGA
Date : 2025-09-19 Size : 2.9mb User : luis
MHLtest Downloaded：0: design of a simple CPU
Date : 2025-09-19 Size : 20.62mb User : 马红丽

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