VHDL-FPGA-Verilog List Page 1965

VHDL-FPGA-Verilog list

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Graphic_LCD Downloaded：0: Monochrome Display driver
Date : 2025-09-19 Size : 10kb User : sreeharsha
CPLD Downloaded：0: verilog written addition and subtraction 6 way reversible counter for FPGA on the 6-channel pulse count
Date : 2025-09-19 Size : 939kb User : zhangshaobo
lcd_dsp Downloaded：0: verilog prepared by the serial and the LCD driver program. FPGA receives serial data, and then in the liquid crystal display, with the black gold development board.
Date : 2025-09-19 Size : 24.11mb User : zhangshaobo
labd3_adc Downloaded：0: PIC ADC LCD converter
Date : 2025-09-19 Size : 16kb User : Sarunas
VGA Downloaded：0: vhdl implementation VGA interface displays four patterns: horizontal color bar, vertical color bars, checkerboard, black and white. File contains four modules: clk_div2- divided by two (input 50Mhz output 25Mhz), makecol
Date : 2025-09-19 Size : 2kb User : zhanghuan
Digital-Clock Downloaded：0: Digital Clock in the FPGA
Date : 2025-09-19 Size : 1.41mb User : lichenhai
Program Downloaded：0: Design a state machine in VHDL 8-bit serial signal detector.
Date : 2025-09-19 Size : 1kb User : 釉雪Dreamer
Program2 Downloaded：0: The 8-bit pre-measured as the number of external input signal, which can change at any time in the sequence comparison of the data detector. Write the symbol of this process a single process finite state machine.
Date : 2025-09-19 Size : 1kb User : 釉雪Dreamer
Program3 Downloaded：0: Design with vhdl language display 8-bit digital scanning circuit, display output data are given directly in the program. Increased eight 4-bit latch display data buffer as the output from the external input 8 to be displ
Date : 2025-09-19 Size : 1kb User : 釉雪Dreamer
Program Downloaded：0: Design an 8-bit digital divider, the 8-bit prescaler extended to 16-bit CNC CNC divider.
Date : 2025-09-19 Size : 1kb User : 釉雪Dreamer
Program5 Downloaded：0: Design an 8-bit digital divider, the 8-bit prescaler extended to 16-bit CNC CNC divider.
Date : 2025-09-19 Size : 1kb User : 釉雪Dreamer
Program6 Downloaded：0: With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter decimal addition and subtraction.
Date : 2025-09-19 Size : 1kb User : 釉雪Dreamer

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