Clock 1Hz with duty cycle control for verilog for DE2-115 Altera FPGA

clock_1Hz
.........\clock_1hz.asm.rpt
.........\clock_1hz.cdf
.........\clock_1hz.done
.........\clock_1hz.dpf
.........\clock_1hz.eda.rpt
.........\clock_1hz.fit.rpt
.........\clock_1hz.fit.summary
.........\clock_1hz.flow.rpt
.........\clock_1hz.map.rpt
.........\clock_1hz.map.summary
.........\clock_1hz.pin
.........\clock_1hz.qpf
.........\clock_1hz.qsf
.........\clock_1hz.qsf.bak
.........\clock_1hz.sof
.........\clock_1hz.sta.rpt
.........\clock_1hz.sta.summary
.........\clock_1hz.v
.........\clock_1hz.v.bak
.........\clock_1hz_description.txt
.........\clock_1hz_nativelink_simulation.rpt
.........\db
.........\..\clock_1hz.amm.cdb
.........\..\clock_1hz.asm.qmsg
.........\..\clock_1hz.asm.rdb
.........\..\clock_1hz.asm_labs.ddb
.........\..\clock_1hz.cbx.xml
.........\..\clock_1hz.cmp.bpm
.........\..\clock_1hz.cmp.cdb
.........\..\clock_1hz.cmp.hdb
.........\..\clock_1hz.cmp.kpt
.........\..\clock_1hz.cmp.logdb
.........\..\clock_1hz.cmp.rdb
.........\..\clock_1hz.cmp_merge.kpt
.........\..\clock_1hz.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.........\..\clock_1hz.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
.........\..\clock_1hz.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
.........\..\clock_1hz.db_info
.........\..\clock_1hz.eda.qmsg
.........\..\clock_1hz.fit.qmsg
.........\..\clock_1hz.hier_info
.........\..\clock_1hz.hif
.........\..\clock_1hz.idb.cdb
.........\..\clock_1hz.lpc.html
.........\..\clock_1hz.lpc.rdb
.........\..\clock_1hz.lpc.txt
.........\..\clock_1hz.map.bpm
.........\..\clock_1hz.map.cdb
.........\..\clock_1hz.map.hdb
.........\..\clock_1hz.map.kpt
.........\..\clock_1hz.map.logdb
.........\..\clock_1hz.map.qmsg
.........\..\clock_1hz.map_bb.cdb
.........\..\clock_1hz.map_bb.hdb
.........\..\clock_1hz.map_bb.logdb
.........\..\clock_1hz.pre_map.cdb
.........\..\clock_1hz.pre_map.hdb
.........\..\clock_1hz.rtlv.hdb
.........\..\clock_1hz.rtlv_sg.cdb
.........\..\clock_1hz.rtlv_sg_swap.cdb
.........\..\clock_1hz.sgdiff.cdb
.........\..\clock_1hz.sgdiff.hdb
.........\..\clock_1hz.sld_design_entry.sci
.........\..\clock_1hz.sld_design_entry_dsc.sci
.........\..\clock_1hz.smart_action.txt
.........\..\clock_1hz.sta.qmsg
.........\..\clock_1hz.sta.rdb
.........\..\clock_1hz.sta_cmp.7_slow_1200mv_85c.tdb
.........\..\clock_1hz.syn_hier_info
.........\..\clock_1hz.tis_db_list.ddb
.........\..\clock_1hz.tiscmp.fast_1200mv_0c.ddb
.........\..\clock_1hz.tiscmp.slow_1200mv_0c.ddb
.........\..\clock_1hz.tiscmp.slow_1200mv_85c.ddb
.........\..\clock_1hz.tmw_info
.........\..\logic_util_heursitic.dat
.........\..\prev_cmp_clock_1hz.qmsg
.........\incremental_db
.........\..............\compiled_partitions
.........\..............\...................\clock_1hz.db_info
.........\..............\...................\clock_1hz.root_partition.cmp.cdb
.........\..............\...................\clock_1hz.root_partition.cmp.dfp
.........\..............\...................\clock_1hz.root_partition.cmp.hdb
.........\..............\...................\clock_1hz.root_partition.cmp.kpt
.........\..............\...................\clock_1hz.root_partition.cmp.logdb
.........\..............\...................\clock_1hz.root_partition.cmp.rcfdb
.........\..............\...................\clock_1hz.root_partition.map.cdb
.........\..............\...................\clock_1hz.root_partition.map.dpi
.........\..............\...................\clock_1hz.root_partition.map.hbdb.cdb
.........\..............\...................\clock_1hz.root_partition.map.hbdb.hb_info
.........\..............\...................\clock_1hz.root_partition.map.hbdb.hdb
.........\..............\...................\clock_1hz.root_partition.map.hbdb.sig
.........\..............\...................\clock_1hz.root_partition.map.hdb
.........\..............\...................\clock_1hz.root_partition.map.kpt
.........\..............\README
.........\simulation
.........\..........\modelsim
.........\..........\........\clock_1hz.sft
.........\..........\........\clock_1hz.vho
.........\..........\........\clock_1hz_7_1200mv_0c

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