Quick test to handle VGA monitor enabling four colors on screen, Verilog Code Source using internal 50MHz clock signal.

.lso
ColorDecoder.v
ColorEnableLin.v
ColorEnablePix.cmd_log
ColorEnablePix.lso
ColorEnablePix.prj
ColorEnablePix.stx
ColorEnablePix.syr
ColorEnablePix.v
ColorEnablePix.xst
ColorEnablePix_summary.html
Cont_Pulse.ngc
Cont_Pulse.ngr
Cont_Pulse.v
Cont_Pulse_summary.html
device_usage_statistics.html
monitor.bgn
monitor.bit
Monitor.bld
Monitor.cmd_log
monitor.drc
Monitor.ise
Monitor.ise_ISE_Backup
Monitor.lfp
Monitor.lso
Monitor.ncd
Monitor.ngc
Monitor.ngd
Monitor.ngr
Monitor.ntrc_log
Monitor.pad
Monitor.par
Monitor.pcf
Monitor.prj
Monitor.restore
Monitor.stx
Monitor.syr
monitor.twr
monitor.twx
Monitor.ucf
Monitor.unroutes
Monitor.ut
Monitor.v
Monitor.xpi
Monitor.xst
Monitor_guide.ncd
Monitor_map.map
Monitor_map.mrp
Monitor_map.ncd
Monitor_map.ngm
Monitor_pad.csv
Monitor_pad.txt
Monitor_prev_built.ngd
Monitor_summary.html
Monitor_summary.xml
Monitor_usage.xml
Pulse.v
Test01.ant
Test01.fdo
Test01.jhd
Test01.tbw
Test01.udo
Test01.xwv
Test01.xwv_bak
Test01_bencher.prj
Test02.ant
Test02.fdo
Test02.jhd
Test02.tbw
Test02.udo
Test02.xwv
Test02.xwv_bak
Test02_bencher.prj
Test03.ant
Test03.fdo
Test03.jhd
Test03.tbw
Test03.tfw
Test03.udo
Test03.xwv
Test03.xwv_bak
Test03_bencher.prj
timing.twr
tmpRTVStore.xwv
transcript
vsim.wlf
work
....\@color@enable@lin
....\.................\verilog.psm
....\.................\_primary.dat
....\.................\_primary.dbs
....\.................\_primary.vhd
....\@color@enable@pix
....\.................\verilog.psm
....\.................\_primary.dat
....\.................\_primary.dbs
....\.................\_primary.vhd
....\@cont_@pulse
....\............\verilog.psm
....\............\_primary.dat

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