VHDL-FPGA-Verilog List Page 1871

VHDL-FPGA-Verilog list

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STC12C5A60S2_UART2 Downloaded：1: UART2 test UART2 test UART2 test UART2 test UART2 test UART2 test.
Date : 2025-09-18 Size : 35kb User : johnnyp
LEDJZ Downloaded：0: Macro crystalline matrix keyboard microcontroller program STC12C5A60S2 latest model has been verified to run correctly.
Date : 2025-09-18 Size : 1kb User : lhf
vhdl Downloaded：0: VHDL clock
Date : 2025-09-18 Size : 4kb User : tao
FPGA-qiangdaqisheji Downloaded：0: based on FPGA　to seize time
Date : 2025-09-18 Size : 5.12mb User : 王涛
cpu_fsm.tar Downloaded：0: write or reset or read or delay of CPU by verilog
Date : 2025-09-18 Size : 49kb User : bob
t33 Downloaded：0: Traffic light control system A main road and a junction with a cross made of branches trunks. According to Commission Meter, main road traffic to slip twice. Requirements: 1), under normal circumstances, re
Date : 2025-09-18 Size : 2kb User : 胡芳洲
LightExp Downloaded：0: LightExp code
Date : 2025-09-18 Size : 1kb User : 正体不明
PROTEUS Downloaded：0: a good book，you can take a try，it is for new men。
Date : 2025-09-18 Size : 2.36mb User : 王建宁
filter Downloaded：0: Digital filter 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
Date : 2025-09-18 Size : 197kb User :
obnar1 Downloaded：0: Digital detector (a-type) 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
Date : 2025-09-18 Size : 206kb User :
obnar3 Downloaded：0: Digital detector (b-type) 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
Date : 2025-09-18 Size : 187kb User :
stopwatch Downloaded：0: failed to translate
Date : 2025-09-18 Size : 1kb User : 王红阳

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