VHDL-FPGA-Verilog List Page 1870

VHDL-FPGA-Verilog list

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Chapter-1 Downloaded：0: • Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Alte
Date : 2025-09-18 Size : 2kb User : shixiaodong
Chapter-2 Downloaded：0: • Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Alte
Date : 2025-09-18 Size : 5kb User : shixiaodong
Chapter-3 Downloaded：0: • Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Alte
Date : 2025-09-18 Size : 4kb User : shixiaodong
Chapter-4 Downloaded：0: • Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Alte
Date : 2025-09-18 Size : 7kb User : shixiaodong
Chapter-5 Downloaded：0: • Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Alte
Date : 2025-09-18 Size : 15kb User : shixiaodong
2DPSK Downloaded：0: Digital phase modulation is also known as phase shift keying, 2DPSK is binary differential phase shift keying, is a kind of digital phase modulation. Digital phase modulation using carrier phase change to transmit digita
Date : 2025-09-18 Size : 1.82mb User : 乐逍遥
Chapter-6 Downloaded：0: • Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Alte
Date : 2025-09-18 Size : 3kb User : shixiaodong
Chapter-7 Downloaded：0: • Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Alte
Date : 2025-09-18 Size : 7kb User : shixiaodong
Chapter-8 Downloaded：0: • Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Alte
Date : 2025-09-18 Size : 328kb User : shixiaodong
DE2-user-Manual-(Chinese-edition) Downloaded：0: DE2 user Manual (Chinese edition)
Date : 2025-09-18 Size : 5.48mb User : googller
uart_verilog Downloaded：0: edited in verilog language
Date : 2025-09-18 Size : 9kb User : gofee
div3 Downloaded：0: This used for divide the frequency,and the duty cycle is 50 .
Date : 2025-09-18 Size : 255kb User :

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