VHDL-FPGA-Verilog List Page 1867

VHDL-FPGA-Verilog list

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voice Downloaded：0: DE2-based project about the input audio and its spectrum on VGA
Date : 2025-09-18 Size : 2.15mb User : 刘毅
Software-Defined-Radio-for-OFDM-Transceivers Downloaded：0: Software-Defined Radio for OFDM Transceivers
Date : 2025-09-18 Size : 874kb User : saravanan k p
lcd Downloaded：0: Suitable for the cortexM3 12864 LCD program. Through testing, it is to use. Including all general display function of the required function, can be realized just need to invoke to function.
Date : 2025-09-18 Size : 4.15mb User : 张宁
verilog_Digital-tube-scanning Downloaded：0: Written imitation of the order of thinking digital scanning, divided into top-level module, the data generation module, the data transfer mode Block, digital scanning module, straightforward and easy to understand.
Date : 2025-09-18 Size : 2kb User : woxx
AudioFilter8khzCodec Downloaded：0: important Audio Filter 8khz Coding
Date : 2025-09-18 Size : 2.25mb User : saravanan k p
VHDL Downloaded：0: 5bit adder
Date : 2025-09-18 Size : 133kb User : 张大人
easy_vhdl Downloaded：0: Some common VHDL code, including logic gates, register, decoder, data selector, trigger, etc.
Date : 2025-09-18 Size : 1kb User : 张大人
SSALU Downloaded：0: VHDL design eight the arithmetic/logic unit (alu), realize the reset, logic, logic and, by different or, arithmetic and logic, logical moves left a, logic move to the right a etc.
Date : 2025-09-18 Size : 1.42mb User : kzelf
C Downloaded：0: C language code base, calculated by adding together and, more streamlined code, in line with the beginner level
Date : 2025-09-18 Size : 1kb User : 张大人
FIFO-verilog Downloaded：0: In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write
Date : 2025-09-18 Size : 326kb User : 肖波
costas Downloaded：0: Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
Date : 2025-09-18 Size : 5kb User : 洪依
da_filter Downloaded：0: DA, distributed algorithm of FILTER FILTER design, verilog design and implementation
Date : 2025-09-18 Size : 2kb User : 洪依

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