VHDL-FPGA-Verilog List Page 1864

VHDL-FPGA-Verilog list

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bcd7seg Downloaded：0: bcd to 7-segment decoder
Date : 2025-09-17 Size : 1kb User : kilhyun
digitalclk Downloaded：0: make use of language of maxplus to make a clock.include day,hour,minute,second
Date : 2025-09-17 Size : 369kb User : 文艺成
vhdl--eda Downloaded：0: failed to translate
Date : 2025-09-17 Size : 2kb User : kuwait
UPLOAD Downloaded：0: BASIC AND GATE OF 3 INPUT & 4,8 AND 16 DECODER
Date : 2025-09-17 Size : 3kb User : ANKIT R SOLANKI
Multi-functional-digital-clock Downloaded：0: Multi-functional digital clock Clock display Manual timing Hourly Chime
Date : 2025-09-17 Size : 360kb User : lee
RS-decoder Downloaded：0: RS decoder includes the following five main parts: With style, calculated error location and error value polynomial, Calculated error location search of money
Date : 2025-09-17 Size : 509kb User : lee
Vending-machine Downloaded：0: Vending machines designed to sell three price of goods. Achieve the basic functions of sales
Date : 2025-09-17 Size : 550kb User : lee
High-Voltage-Generator Downloaded：0: This source can used to design a high-voltage supply by used the chip of UC3845.
Date : 2025-09-17 Size : 396kb User : 陈盼辉
fft_16 Downloaded：0: 16 points of the fft program, the entrance parameters (input data, output data)
Date : 2025-09-17 Size : 2kb User : 木偶然
adc_correct13 Downloaded：0: AD correct
Date : 2025-09-17 Size : 3kb User : 刘莹
jiafaqi Downloaded：0: half-adder and full-adder
Date : 2025-09-17 Size : 1kb User : shiyun
cpu_supplement Downloaded：0: RTEMS CPU Architecture Supplement
Date : 2025-09-17 Size : 214kb User : tsn

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