VHDL-FPGA-Verilog List Page 1747

VHDL-FPGA-Verilog list

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synchronism_design Downloaded：0: often will be in the fpga experience across clock or asynchronous clock, which relates to clock synchronization issues
Date : 2025-09-16 Size : 61kb User : 磨国钰
edge_tech_design Downloaded：0: the verilog edge detection technology, in fpga signal processing is quite large, and this is an art
Date : 2025-09-16 Size : 37kb User : 磨国钰
uart_fifo_design Downloaded：0: On the uart PC debug FIFO communication design, designed after n times of 1024 numerous times to send no bug
Date : 2025-09-16 Size : 179kb User : 磨国钰
PS2 Downloaded：0: PS2 program-the keyboard to send a button through the register will be the ASCI coding convert hex in digital tube display-I have in LYC FREE EDA development board through verification
Date : 2025-09-16 Size : 346kb User : 刘
FPGA_atel2_bin Downloaded：0: FPGA and MCU serial design, source
Date : 2025-09-16 Size : 59kb User :
FPGA_DDR-SDRAM Downloaded：0: FPGA SDRAM control, part of the source,
Date : 2025-09-16 Size : 5.15mb User :
Logic-analyzer Downloaded：0: A logic analyzer source development, including single-chip FPGA All Programs, and hardware schematics
Date : 2025-09-16 Size : 10.93mb User :
my_counter10_test2 Downloaded：0: decimal counter
Date : 2025-09-16 Size : 226kb User : yang
lab01_2 Downloaded：0: group of registers MIPS
Date : 2025-09-16 Size : 4.99mb User : 周钇驰
wenjian Downloaded：0: PPMmodulation in visiable lighting communication system，VHDL FPGA
Date : 2025-09-16 Size : 7.11mb User : 魏玉龙
lock Downloaded：0: The program is a digital code lock function, when the correct password is entered to unlock, if the input error will alarm
Date : 2025-09-16 Size : 958kb User : 张扬
music Downloaded：0: The program to achieve the function of music player, music is the default, the principle is driven by different frequencies buzzer to send the different scales
Date : 2025-09-16 Size : 2.36mb User : 张扬

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