VHDL-FPGA-Verilog List Page 1744

VHDL-FPGA-Verilog list

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VHDLBasicExperimentSJTU Downloaded：0: Shanghai Jiaotong University and a few experiments of basic VHDL code, including the frequency divider, timer, seven segment counter, state machines, latches, etc.
Date : 2025-09-16 Size : 845kb User : 魏玉萍
v8_ID-12345678 Downloaded：0: JLINK v8
Date : 2025-09-16 Size : 26kb User : xxxxx
ThBird Downloaded：0: Thunderbird car taillight design, using VERILOG language, everyone can become familiar with the state machine experiment.
Date : 2025-09-16 Size : 396kb User : 仲崇鑫
ShiftReg Downloaded：0: Arithmetic shift register and logic shift register of simple design, containing a detailed description.
Date : 2025-09-16 Size : 435kb User : 仲崇鑫
counter Downloaded：0: Counter VHDL programming code
Date : 2025-09-16 Size : 200kb User : 张双锋
liushuideng Downloaded：0: By using VHDL program language programming to realize the function of light water
Date : 2025-09-16 Size : 276kb User : 张双锋
decode38 Downloaded：0: Through the use of VHDL language programming to achieve the 38 decoder functions
Date : 2025-09-16 Size : 115kb User : 张双锋
bit1_add Downloaded：0: Through the use of VHDL language programming experiment 1 and a half adder function
Date : 2025-09-16 Size : 103kb User : 张双锋
div_sim Downloaded：0: Through the use of VHDL language procedures for the realization of the divider function
Date : 2025-09-16 Size : 112kb User : 张双锋
digitai-clock Downloaded：0: Through the use of VHDL language procedures for the realization of the digital clock function
Date : 2025-09-16 Size : 409kb User : 张双锋
Counter Downloaded：0: With the VERILOG language implementation of the 74* 163 counter, the code is very simple and easy to understand, suitable for digital logic circuit experiment for beginners
Date : 2025-09-16 Size : 406kb User : 仲崇鑫
yuv444_rgb888 Downloaded：0: Implementation of YUV444 RGB888, has passed the Verilog authentication!
Date : 2025-09-16 Size : 2.86mb User : zhaijiong

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