Through the use of VHDL language procedures for the realization of the divider function

div_sim\db\add_sub_4rh.tdf
.......\..\div_sim.cbx.xml
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.......\..\div_sim.cmp_merge.kpt
.......\..\div_sim.db_info
.......\..\div_sim.eco.cdb
.......\..\div_sim.eds_overflow
.......\..\div_sim.fnsim.cdb
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.......\..\div_sim.fnsim.qmsg
.......\..\div_sim.hier_info
.......\..\div_sim.hif
.......\..\div_sim.lpc.html
.......\..\div_sim.lpc.rdb
.......\..\div_sim.lpc.txt
.......\..\div_sim.map.bpm
.......\..\div_sim.map.cdb
.......\..\div_sim.map.ecobp
.......\..\div_sim.map.hdb
.......\..\div_sim.map.kpt
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.......\..\div_sim.rtlv.hdb
.......\..\div_sim.rtlv_sg.cdb
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.......\..\div_sim.sgdiff.cdb
.......\..\div_sim.sgdiff.hdb
.......\..\div_sim.sim.hdb
.......\..\div_sim.sim.qmsg
.......\..\div_sim.sim.rdb
.......\..\div_sim.simfam
.......\..\div_sim.sim_ori.vwf
.......\..\div_sim.sld_design_entry.sci
.......\..\div_sim.sld_design_entry_dsc.sci
.......\..\div_sim.smart_action.txt
.......\..\div_sim.syn_hier_info
.......\..\div_sim.tis_db_list.ddb
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_div_sim.map.qmsg
.......\..\prev_cmp_div_sim.qmsg
.......\..\prev_cmp_div_sim.sim.qmsg
.......\..\wed.wsf
.......\div_sim.done
.......\div_sim.flow.rpt
.......\div_sim.map.rpt
.......\div_sim.map.summary
.......\div_sim.qpf
.......\div_sim.qsf
.......\div_sim.qws
.......\div_sim.sim.rpt
.......\div_sim.vhd
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.......\div_sim.vwf
.......\incremental_db\compiled_partitions\div_sim.root_partition.map.cdb
.......\..............\...................\div_sim.root_partition.map.dpi
.......\..............\...................\div_sim.root_partition.map.hdb
.......\..............\...................\div_sim.root_partition.map.kpt
.......\..............\README
.......\..............\compiled_partitions
.......\db
.......\incremental_db
div_sim

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