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VHDL-FPGA-Verilog list
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FPGA_27demos
Downloaded:0
Some of the basic instance based on fpga, practicability, module can be used directly
Date
: 2025-09-16
Size
: 1.22mb
User
:
张志勇
baoshi
Downloaded:0
(1) when the timer operation to 59 49 seconds to strike the start point, each named 1 s stop call 1 s, resonance that six ring, before 5 ring for bass, frequency for 740 Hz Finally a ring for high notes, frequency for 1
Date
: 2025-09-16
Size
: 38kb
User
:
郭慧
guangbobaoshi
Downloaded:0
) when the timer operation to 59 49 seconds to strike the start point, each named 1 s stop call 1 s, resonance that six ring, before 5 ring for bass, frequency for 740 Hz Finally a ring for high notes, frequency for 1 KH
Date
: 2025-09-16
Size
: 38kb
User
:
郭慧
Quick51jump
Downloaded:0
quick51 jump
Date
: 2025-09-16
Size
: 13kb
User
:
王正
FPL2010_v20100901_publicado
Downloaded:0
Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA.
Date
: 2025-09-16
Size
: 573kb
User
:
fangjiali
clock
Downloaded:0
Implemented digital electronic clock function, including, points, seconds, can show
Date
: 2025-09-16
Size
: 1.42mb
User
:
张扬
channel_fir
Downloaded:0
Used for wireless digital baseband channel selection filter, verilog code
Date
: 2025-09-16
Size
: 4kb
User
:
黄巾
vhdl
Downloaded:0
Electronic clock and alarm, vhdl language program structure is compact, very quickly due to the FPGA clock, the clock is very accurate
Date
: 2025-09-16
Size
: 179kb
User
:
蔡国峰
pie_encode
Downloaded:0
The agreement with EPC C1G2 digital baseband PIE coding module source code
Date
: 2025-09-16
Size
: 1kb
User
:
黄巾
clk_gen
Downloaded:0
The agreement with EPC C1G2 digital baseband global synchronous clock produces module source code
Date
: 2025-09-16
Size
: 2kb
User
:
黄巾
crc
Downloaded:0
The agreement with EPC C1G2 digital baseband crc verify module source code
Date
: 2025-09-16
Size
: 2kb
User
:
黄巾
clock-design-verilog-Fpga
Downloaded:0
using verilog design watch, digital circuit design, FPGA
Date
: 2025-09-16
Size
: 1.46mb
User
:
Nee
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4310
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