using verilog design watch, digital circuit design, FPGA

数字时钟设计\lab.qpf
............\lab.qsf
............\db\lab.db_info
............\..\lab.cbx.xml
............\..\lab.map_bb.hdbx
............\..\prev_cmp_lab.qmsg
............\..\prev_cmp_lab.map.qmsg
............\..\lab.sld_design_entry.sci
............\..\lab.eco.cdb
............\..\lab.map.qmsg
............\..\lab.hif
............\..\lab.hier_info
............\..\lab.rtlv_sg.cdb
............\..\lab.rtlv.hdb
............\..\lab.rtlv_sg_swap.cdb
............\..\lab.pre_map.hdb
............\..\lab.pre_map.cdb
............\..\lab.psp
............\..\lab.root_partition.map.info
............\..\lpm_divide_25m.tdf
............\..\sign_div_unsign_9kh.tdf
............\..\alt_u_div_kve.tdf
............\..\add_sub_lkc.tdf
............\..\add_sub_mkc.tdf
............\..\lab.map_bb.logdb
............\..\lab.sgdiff.cdb
............\..\lab.sgdiff.hdb
............\..\lab.sld_design_entry_dsc.sci
............\..\lab.syn_hier_info
............\..\lab.root_partition.map.atm
............\..\lab.root_partition.map.hdbx
............\..\lab.map_bb.cdb
............\..\lab.map_bb.hdb
............\..\lab.map.ecobp
............\..\lab.map.cdb
............\..\lab.map.hdb
............\..\lab.map.logdb
............\..\lab.map.bpm
............\..\lab.fit.qmsg
............\..\lab.cmp.logdb
............\..\lab.cmp.bpm
............\..\lab.cmp.ecobp
............\..\lab.root_partition.cmp.rcf
............\..\lab.root_partition.cmp.hdbx
............\..\lab.root_partition.cmp.atm
............\..\lab.root_partition.cmp.logdb
............\..\lab.root_partition.cmp.dfp
............\..\lab.tis_db_list.ddb
............\..\lab.asm.qmsg
............\..\lab.asm_labs.ddb
............\..\lab.tan.qmsg
............\..\lab.cmp.tdb
............\..\lab.cmp0.ddb
............\..\lab.cmp.cdb
............\..\lab.signalprobe.cdb
............\..\lab.cmp.hdb
............\..\lab.cmp.rdb
............\lab5.txt.v
............\lab.map.summary
............\o\lab5.qpf
............\.\lab5.qsf
............\.\db\wed.wsf
............\.\..\lab5.db_info
............\.\..\lab5.sld_design_entry.sci
............\.\..\lab5.cmp0.ddb
............\.\..\lab5.cmp.cdb
............\.\..\lab5.cmp.ecobp
............\.\..\lab5.cmp.hdb
............\.\..\lab5.cmp.rdb
............\.\..\lab5.cmp.bpm
............\.\..\lab5.root_partition.cmp.logdb
............\.\..\lab5.cbx.xml
............\.\..\lab5.root_partition.cmp.dfp
............\.\..\lab5.asm.qmsg
............\.\..\lab5.map_bb.hdbx
............\.\..\lab5.tis_db_list.ddb
............\.\..\lab5.asm_labs.ddb
............\.\..\lab5.tan.qmsg
............\.\..\prev_cmp_lab5.qmsg
............\.\..\lab5.cmp.tdb
............\.\..\lab5.fnsim.qmsg
............\.\..\lab5.signalprobe.cdb
............\.\..\lab5.eco.cdb
............\.\..\lpm_divide_vcm.tdf
............\.\..\prev_cmp_lab5.sim.qmsg
............\.\..\lab5.sim.qmsg
............\.\..\lab5.sim.cvwf
............\.\..\lab5.fnsim.cdb
............\.\..\lab5.hif
............\.\..\lab5.hier_info
............\.\..\lab5.simfam
............\.\..\lab5.fnsim.hdb
............\.\..\lab5.eds_overflow
............\.\..\lab5.sim.rdb
............\.\..\lab5.sim.hdb
............\.\..\lab5.psp
............\.\..\lab5.sld_design_entry_dsc.sci
............\.\..\lpm_divide_25m.tdf
............\.\..\sign_div_unsign_9kh.tdf
............\.\..\alt_u_div_kve.tdf

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