VHDL-FPGA-Verilog List Page 17

VHDL-FPGA-Verilog list

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phone_charge Downloaded：1: Coin-operated mobile phone charger(Another version) It is divided into two parts: time display and amount display. According to the amount of input, it shows twice the time. It can be cleared at any time, determined and
Date : 2025-06-24 Size : 1.78mb User : ctrlwdza
自动售货机 Downloaded：1: Using 1200 PLC to simulate the running process of vending machine
Date : 2025-06-24 Size : 722kb User : singker
数据库 Downloaded：0: 本VI是介绍使用数据库前的配置流程，打开VI，可运行点击下一步浏览Labview在使用数据库的简单步骤！
Date : 2019-07-27 Size : 354.91kb User : xyzttc
pps_ketiao_rb2 Downloaded：0: FPGA program generates 1 PPS pulse signal, using Verilog language.
Date : 2025-06-24 Size : 7.41mb User : 张媛
BPSK Downloaded：0: Firstly, the filter coefficients are obtained by simulation with the theory of matlab. Then the program is written in Verilog language under ISE environment. Waveform simulation and quotation mark grabbing are carried ou
Date : 2025-06-24 Size : 6.43mb User : 财哥在此
svtb_ahb_sram Downloaded：0: abcdefghijklmnopqrstuvwxyz
Date : 2025-06-24 Size : 3.22mb User : fkmeng
S03_基于ZYNQ的DMA与VDMA的应用开发 Downloaded：0: vivado DMA&VDMA example text of zynq
Date : 2025-06-24 Size : 9.24mb User : kernelstory
S04_基于ZYNQ的HLS 图像算法设计基础 Downloaded：0: vivado image processing example text of zynq
Date : 2025-06-24 Size : 7.63mb User : kernelstory
S05_example_Network Downloaded：1: vivado lwip example text of zynq
Date : 2025-06-24 Size : 3.24mb User : kernelstory
sram Downloaded：0: Read and write SRAM memory block and Verilog code in FPGA
Date : 2025-06-24 Size : 1.32mb User : bin_mm3
verilog实现dds Downloaded：1: The function of signal generator is realized based on FPGA, which is a good reference.
Date : 2025-06-24 Size : 2.47mb User : sudochang
Rs通用编码 Downloaded：0: 适用各种体制的RS编码，Verilog实现，配置本原多项式参数即可
Date : 2019-08-29 Size : 1.71kb User : 1314@someone

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