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Verilog Digital VLSI Design Course Official Lab
Date : 2025-06-25 Size : 10.95mb User : brico

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The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.
Date : 2025-06-25 Size : 1kb User : wrnd

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The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the data range of simulation weight in the
Date : 2025-06-25 Size : 928kb User : SEXYLADY

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Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width of 8bits, symbol rate of 16MHz Requirements in Matlab FIR filter floating-point and fixed-point simulation, an
Date : 2025-06-25 Size : 334kb User : 羊羊驼

Design a 1MHz FIR low pass filter. Huffman coding is required for a section of data sequence to make the average code length the shortest, and the output of each element encoding and the encoded data sequence. The elemen
Date : 2025-06-25 Size : 178kb User : 羊羊驼

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Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code
Date : 2025-06-25 Size : 7kb User : frostmorne

Solutions for computer experiment.
Date : 2025-06-25 Size : 33.2mb User : 陈惜

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rgb to YCbCr converter
Date : 2025-06-25 Size : 4.61mb User : Kevaen

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Program for sending data from computer and receiving data by FPGA, UART module
Date : 2025-06-25 Size : 17.55mb User : godxun

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Verilog code writing and simulation files for brick-blocking games
Date : 2025-06-25 Size : 6kb User : simplewqq

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The DE2-115 board is shipped from the factory with a default configuration bit-stream that demonstrates some of the basic features of the board.
Date : 2025-06-25 Size : 3.01mb User : 流火守夜人

Xilinx USB driver for win10, newer version
Date : 2025-06-25 Size : 459kb User : yuyangfei
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