[VHDL-FPGA-Verilog] 通信协议FPGA

Description: This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIF
Platform: | Size: 19605504 | Author: 蔺娇娇 | Hits:

[VHDL-FPGA-Verilog] new

Description: Accelerometers adxl357 read the acceleration value of XYZ three-axis direction through SPI
Platform: | Size: 5120 | Author: LJHER | Hits:

[VHDL-FPGA-Verilog] basketball_24time1

Description: This document mainly uses Verilog language to realize basketball 24 second timer, which is a big assignment of digital electronic technology course I do. It contains the entire folder. After decompression, it can be run
Platform: | Size: 5646336 | Author: 1003512666 | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet M
Platform: | Size: 1024 | Author: liyan2020 | Hits:

[VHDL-FPGA-Verilog] ac620_calculator_key_board

Description: The calculator based on Verilog uses matrix keyboard to input data and digital tube to display the operation process and results. The development board based on little mac620 passed the verification
Platform: | Size: 40960 | Author: 小梅哥fpga | Hits:

[VHDL-FPGA-Verilog] FPGA实现Jpeg压缩，和视频采集程序

Description: Zynq - Main - register access Mio
Platform: | Size: 103424 | Author: kongqiweiliang | Hits:

[VHDL-FPGA-Verilog] 基于FPGA的多路同步脉冲发生器设计1

Description: Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide the frequency of the signal, to achieve the four-way signal phase difference T / 16 and
Platform: | Size: 10240 | Author: 哈哈哈哈daxiao | Hits:

[VHDL-FPGA-Verilog] vivado2018+IPs

Description: Xilinx Vivado 2018 License File
Platform: | Size: 4096 | Author: Indus_Floyd | Hits:

[VHDL-FPGA-Verilog] DDR2_SDRAM操作时序

Description: DDR2? SDRAM operation sequence, very detailed introduction, very good
Platform: | Size: 1936384 | Author: zou3 | Hits:

[VHDL-FPGA-Verilog] led_test.v

Description: show a water led show a water led show a water led show a water led show a water led
Platform: | Size: 759 | Author: rbvikg | Hits:

[VHDL-FPGA-Verilog] verilog实例 [43项]

Description: Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning
Platform: | Size: 190464 | Author: hayto | Hits:

[VHDL-FPGA-Verilog] SPI_UVM_VIP

Description: Chip verification VIP of SPI protocol, build platform verification code with UVM
Platform: | Size: 5477376 | Author: lfzero | Hits: