[VHDL-FPGA-Verilog] 国产FPGA参考设计IPCORE_UART_example_M5&M7

Description: The IP provides two kinds of simplified interface connected to EMIF bus and AHB bus for communication with 8051 core and ARM core.The two kinds of interface are full-duplex serial communication interface.
Platform: | Size: 3162112 | Author: 空空居士 | Hits:

[VHDL-FPGA-Verilog] 单周期CPU大作业-2020

Description: Verilog projects cpu
Platform: | Size: 889856 | Author: sast | Hits:

[VHDL-FPGA-Verilog] POC

Description: It simulates the POC module which works as an I/O module in a computer system.
Platform: | Size: 3072 | Author: 青空空 | Hits:

[VHDL-FPGA-Verilog] drsstc

Description: DRSSTC project file for SKP / PDM
Platform: | Size: 4096 | Author: 氧化钙yhg | Hits:

[VHDL-FPGA-Verilog] 4乘4键盘扫描控制器

Description: 1. The key value is encoded in hexadecimal, i.e. 16 keys display hexadecimal numbers respectively 0 ~ F, the corresponding relationship of keys is as follows: the top line is 0 ~ 3 from left to right, The second row is 4
Platform: | Size: 3444736 | Author: Minbadly | Hits:

[VHDL-FPGA-Verilog] 0-999随机数

Description: 1. Design and implement a random number generating circuit, which generates randomly every 2 seconds Form a number between 0 and 999 and display it on the nixie tube Generated random number. 2. Set a reset key for the sy
Platform: | Size: 4747264 | Author: Minbadly | Hits:

[VHDL-FPGA-Verilog] CNN

Description: a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed
Platform: | Size: 1805312 | Author: gothic22 | Hits:

[VHDL-FPGA-Verilog] 双电梯控制器

Description: a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed
Platform: | Size: 250880 | Author: gothic22 | Hits:

[VHDL-FPGA-Verilog] Verilog的150个经典设计实例

Description: 150 classic programming examples of Verilog
Platform: | Size: 113664 | Author: 叫我小白呀 | Hits:

[VHDL-FPGA-Verilog] DPWM

Description: The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer
Platform: | Size: 500736 | Author: lw1997 | Hits:

[VHDL-FPGA-Verilog] crc16

Description: CRC verification in Verilog: CRC 16
Platform: | Size: 3072 | Author: suncrystal | Hits:

[VHDL-FPGA-Verilog] 8层电梯控制器

Description: there are eight input buttons in the elevator to respond to the user's request for going up and down the floor
Platform: | Size: 1684480 | Author: wtq0 | Hits: