VHDL-FPGA-Verilog List Page 1557

VHDL-FPGA-Verilog list

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nios2_flash_programmer Downloaded：0: Details nios2 how to use the flash programming, as well as step by step explain how to use the IDE environment
Date : 2025-09-13 Size : 428kb User : 李立鸣
h.264_vhdl Downloaded：0: Base Profile level H.264 encoder IP core, code comments in considerable detail, the process is clear
Date : 2025-09-13 Size : 51kb User : 李立鸣
divider Downloaded：0: With the rapid verilog write except machines (eight divided by four)
Date : 2025-09-13 Size : 87kb User : pigerzhu
EPM7064-SR-Motor Downloaded：0: CPLD EPM7064，to control SR motor
Date : 2025-09-13 Size : 340kb User : jipanpan
test_parallel_dds Downloaded：0: The control signals of the chip are asserted by the FPGA chip on the // core board completely. If the FPGA chip is configured properly and // there is no wrong connection, you can see a sine wave
Date : 2025-09-13 Size : 423kb User : Owen
PLD Downloaded：0: PLD language and simple design. We want to help.
Date : 2025-09-13 Size : 7.02mb User : linhuiying
hamming-code Downloaded：0: Contains four modules, namely (1) 16 sequence generation and grouping module (2) encoding module (3) wrong module (4) decoding and packet serial
Date : 2025-09-13 Size : 3kb User : whywhy
clock Downloaded：0: the clock of verilog
Date : 2025-09-13 Size : 839kb User : 肖焕
EDA Downloaded：0: A binary full-cut design and mold variable counter design with VHDL programming
Date : 2025-09-13 Size : 225kb User : 高华
EDA1 Downloaded：0: VHDL programming sequence signal generator and detector design and the design of the digital clock
Date : 2025-09-13 Size : 254kb User : 高华
shiyanwu Downloaded：0: VHDL programming to a main road, a country road. Composed of a crossroads, requiring priority to ensuring the main road traffic. MR (red), MY (main yellow), MG (green), CR (Township red), CY (Township yellow), CG (Townsh
Date : 2025-09-13 Size : 133kb User : 高华
Moore_Asynchronous_state_machine Downloaded：0: the moore asynchronous state machine verilog implementation, asynchronous clock and two input to the output state control, have a much wider application than the synchronous state machine.
Date : 2025-09-13 Size : 191kb User : 李莫

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