VHDL-FPGA-Verilog List Page 1554

VHDL-FPGA-Verilog list

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gray Downloaded：0: a program of ten divider,with a source and test file,using the verilog language
Date : 2025-09-13 Size : 1kb User : Princess
Frequency-meter-design.docx Downloaded：0: P1 or port P3, resulting in a party wave signal, a frequency of 1000Hz LCD displays frequency and cycle 2 output signal input for the frequency of the signal input to another port, to measure frequency, period and pulse
Date : 2025-09-13 Size : 306kb User :
shuzishizhong Downloaded：0: The multi-function digital clock has the following features 1. Sec/min/turn and correct count 2. Regular alarm clock: the whole point of time, the speaker issued a chime sound 3. Time settings manually function: When the
Date : 2025-09-13 Size : 30kb User : 张小白
VHDL Downloaded：0: An active methodology for teaching electronic systems design
Date : 2025-09-13 Size : 9.74mb User : 刘洋
DDS-SIN Downloaded：0: DDS sine wave sent verilog language
Date : 2025-09-13 Size : 2.51mb User : 牛倩
altlvds_DesignExample Downloaded：0: Using FPGA LVDS
Date : 2025-09-13 Size : 203kb User : haifeng
ds18b20 Downloaded：0: ds18b20 program written in verilog
Date : 2025-09-13 Size : 3kb User : iweimo
altlvds_DesignExample_ex2 Downloaded：0: Using FPGA LVDS
Date : 2025-09-13 Size : 113kb User : haifeng
altlvds_DesignExample_ex3 Downloaded：0: Using FPGA LVDS
Date : 2025-09-13 Size : 252kb User : haifeng
altlvds_DesignExample_ex4 Downloaded：0: using fpga lvds
Date : 2025-09-13 Size : 31kb User : haifeng
altlvds_DesignExample_ex5 Downloaded：0: using fpga lvds
Date : 2025-09-13 Size : 12kb User : haifeng
openmsp430_latest.tar Downloaded：1: Open Source MSP430 Core verilog code, for studying.
Date : 2025-09-13 Size : 30.35mb User : Youlong Tao

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