The control signals of the chip are asserted by the FPGA chip on the // core board completely. If the FPGA chip is configured properly and // there is no wrong connection, you can see a sine wave

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.................\DCMIPCore_arwz.ucf
.................\device_usage_statistics.html
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.................\test_parallel_dds.bgn
.................\test_parallel_dds.bit
.................\test_parallel_dds.bld
.................\test_parallel_dds.cmd_log
.................\test_parallel_dds.drc
.................\test_parallel_dds.ise
.................\test_parallel_dds.lso
.................\test_parallel_dds.ncd
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.................\test_parallel_dds.ngd
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.................\test_parallel_dds.pad
.................\test_parallel_dds.par
.................\test_parallel_dds.pcf
.................\test_parallel_dds.prj
.................\test_parallel_dds.ptwx
.................\test_parallel_dds.restore
.................\test_parallel_dds.stx
.................\test_parallel_dds.syr
.................\test_parallel_dds.twr
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.................\test_parallel_dds.unroutes
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.................\test_parallel_dds.v
.................\test_parallel_dds.xpi
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.................\test_parallel_dds_guide.ncd
.................\test_parallel_dds_map.map
.................\test_parallel_dds_map.mrp
.................\test_parallel_dds_map.ncd
.................\test_parallel_dds_map.ngm
.................\test_parallel_dds_map.xrpt
.................\test_parallel_dds_ngdbuild.xrpt
.................\test_parallel_dds_pad.csv
.................\test_parallel_dds_pad.txt
.................\test_parallel_dds_par.xrpt
.................\test_parallel_dds_prev_built.ngd
.................\test_parallel_dds_summary.html
.................\test_parallel_dds_summary.xml
.................\test_parallel_dds_usage.xml
.................\..................xdb\cst.xbcd
.................\.....................\tmp\ise\version
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.................\.....................\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
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.................\.....................\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
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.................\.....................\...\...\............\................\................\NameMap
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.................\.....................\...\...\............\................Gui\GuiProjectData
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.................\.....................\...\...\............\xreport\Gc_RvReportViewer-Current-Module
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.................\.....................\...\...\............\.......\Gc_RvReportViewer-Module-Data-test_parallel_dds
.................\.....................\...\...\............\.......\Gc_RvReportViewer-Module-Data-test_parallel_dds_StrTbl
.................\.....................\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
.................\........

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