VHDL-FPGA-Verilog List Page 1492

VHDL-FPGA-Verilog list

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div Downloaded：0: A divide, a divide counter principle. Very simple, suitable for beginners
Date : 2025-09-12 Size : 1kb User : 郭稳
8-Bit-Simple-Up-Counter Downloaded：0: Simple, counters, and the positive edge. Tested
Date : 2025-09-12 Size : 1kb User : 郭稳
8-Bit-Up-Counter-With-Load Downloaded：0: 8-bit counter, plus or minus count after ise test simulation. Logical
Date : 2025-09-12 Size : 1kb User : 郭稳
Divide-by-2-Counter Downloaded：0: Divide by the counter to achieve very practical, can be used as clock driver.
Date : 2025-09-12 Size : 1kb User : 郭稳
Gray-Counter Downloaded：0: Gray code, the function used to understand and reduce errors. The same for the Karnaugh map.
Date : 2025-09-12 Size : 1kb User : 郭稳
sdram_mdl Downloaded：0: SDRAM FPGA project. Written in Verilog. Device model K4S641632, after the experimental board, absolutely available.
Date : 2025-09-12 Size : 2.47mb User : 李水军
verilogiic1121 Downloaded：0: I2C bus of the FPGA project, Verilog prepared. Program is tested, absolutely available.
Date : 2025-09-12 Size : 376kb User : 李水军
JXJ_TOP Downloaded：0: VHDL language to establish a simple computer engineering, has been tested correctly.
Date : 2025-09-12 Size : 3.93mb User : dean
ps2verilog Downloaded：0: PS2 port of the FPGA project, after testing, is absolutely available.
Date : 2025-09-12 Size : 332kb User : 李水军
uartverilog Downloaded：0: Serial port of the FPGA project, tested, and absolutely available.
Date : 2025-09-12 Size : 305kb User : 李水军
verilogvga Downloaded：0: VGA interface of the FPGA project, Verilog prepared, tested, and absolutely available.
Date : 2025-09-12 Size : 256kb User : 李水军
15_tlc5620dac Downloaded：0: FPGA development project of the DA, DA Model: TLC5620, after I tested, the absolute available
Date : 2025-09-12 Size : 96kb User : 李水军

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