I2C bus of the FPGA project, Verilog prepared. Program is tested, absolutely available.

verilogiic1121\cstate.jpg
..............\db\iic_top.amm.cdb
..............\..\iic_top.cbx.xml
..............\..\iic_top.cmp.bpm
..............\..\iic_top.cmp.cdb
..............\..\iic_top.cmp.hdb
..............\..\iic_top.cmp.kpt
..............\..\iic_top.cmp.logdb
..............\..\iic_top.cmp.rdb
..............\..\iic_top.cmp_merge.kpt
..............\..\iic_top.db_info
..............\..\iic_top.fit.qmsg
..............\..\iic_top.hier_info
..............\..\iic_top.hif
..............\..\iic_top.idb.cdb
..............\..\iic_top.lpc.html
..............\..\iic_top.lpc.rdb
..............\..\iic_top.lpc.txt
..............\..\iic_top.map.bpm
..............\..\iic_top.map.cdb
..............\..\iic_top.map.hdb
..............\..\iic_top.map.kpt
..............\..\iic_top.map.logdb
..............\..\iic_top.map.qmsg
..............\..\iic_top.map_bb.cdb
..............\..\iic_top.map_bb.hdb
..............\..\iic_top.map_bb.logdb
..............\..\iic_top.pre_map.cdb
..............\..\iic_top.pre_map.hdb
..............\..\iic_top.rtlv.hdb
..............\..\iic_top.rtlv_sg.cdb
..............\..\iic_top.rtlv_sg_swap.cdb
..............\..\iic_top.sgdiff.cdb
..............\..\iic_top.sgdiff.hdb
..............\..\iic_top.sld_design_entry.sci
..............\..\iic_top.sld_design_entry_dsc.sci
..............\..\iic_top.smart_action.txt
..............\..\iic_top.smp_dump.txt
..............\..\iic_top.syn_hier_info
..............\..\iic_top.tis_db_list.ddb
..............\..\iic_top.tmw_info
..............\..\iic_top_global_asgn_op.abo
..............\..\logic_util_heursitic.dat
..............\..\prev_cmp_iic_top.asm.qmsg
..............\..\prev_cmp_iic_top.fit.qmsg
..............\..\prev_cmp_iic_top.map.qmsg
..............\..\prev_cmp_iic_top.tan.qmsg
..............\..\wed.wsf
..............\iic_com.v
..............\iic_top.asm.rpt
..............\iic_top.cdf
..............\iic_top.done
..............\iic_top.fit.rpt
..............\iic_top.fit.smsg
..............\iic_top.fit.summary
..............\iic_top.flow.rpt
..............\iic_top.map.rpt
..............\iic_top.map.summary
..............\iic_top.pof
..............\iic_top.qpf
..............\iic_top.qsf
..............\iic_top.qws
..............\iic_top.tan.rpt
..............\iic_top.tan.summary
..............\iic_top.v
..............\iic_top.v.bak
..............\iic_top_assignment_defaults.qdf
..............\.ncremental_db\compiled_partitions\iic_top.db_info
..............\..............\...................\iic_top.root_partition.map.cdb
..............\..............\...................\iic_top.root_partition.map.dpi
..............\..............\...................\iic_top.root_partition.map.hbdb.cdb
..............\..............\...................\iic_top.root_partition.map.hbdb.hb_info
..............\..............\...................\iic_top.root_partition.map.hbdb.hdb
..............\..............\...................\iic_top.root_partition.map.hbdb.sig
..............\..............\...................\iic_top.root_partition.map.hdb
..............\..............\...................\iic_top.root_partition.map.kpt
..............\..............\README
..............\led_seg7.v
..............\tb_iic_top.vwf
..............\incremental_db\compiled_partitions
..............\db
..............\incremental_db
verilogiic1121

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