VHDL-FPGA-Verilog List Page 140

VHDL-FPGA-Verilog list

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kbd Downloaded：0: avr code kbd optimization source code code
Date : 2025-05-19 Size : 49kb User : abbasdf
paral Downloaded：0: verilog avr algorithm avr
Date : 2025-05-19 Size : 7.84mb User : abbasdf
dds6_ise12migration Downloaded：0: With DE2 as the development platform and Veriolg language programming, the DDS signal output, frequency, step and waveform output can be adjusted. The correctness of the design is verified by using Modelsim and FPGA embe
Date : 2025-05-19 Size : 3.25mb User : 小小猪猪猪
crc_verilog_xilinx Downloaded：0: Contains the following files readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : C
Date : 2025-05-19 Size : 10kb User : chris_lj
modelsim入门 Downloaded：0: Modelsim valuable user guide for engineers
Date : 2025-05-19 Size : 5kb User : chris_lj
VHDL Downloaded：0: gennerate SVPWM wave
Date : 2025-05-19 Size : 5kb User : thunder881
Zircon_Digital Downloaded：0: dsfvfdgbgfsbfsbgfsbfbfg
Date : 2025-05-19 Size : 25.53mb User : 南归雁
Zircon_Example Downloaded：0: Very useful for beginners FPGA programming examples, to help beginners less Wuning Road
Date : 2025-05-19 Size : 35.28mb User : 南归雁
ref32 Downloaded：0: An FPGA based human detection system with embedded platform
Date : 2025-05-19 Size : 574kb User : amjadianp
dth Downloaded：0: sdsg er3wresdg test w45 24at eu y t545 4 4t 4
Date : 2025-05-19 Size : 500kb User : moeti
mys-xc7z020-trd Downloaded：0: Zturn Board verilog source. Headless.
Date : 2025-05-19 Size : 7.11mb User : ratfink
mys-xc7z020-lcd-xylon Downloaded：0: Zturn board verilog source with LCD driver.
Date : 2025-05-19 Size : 26.85mb User : ratfink

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