VHDL-FPGA-Verilog List Page 135

VHDL-FPGA-Verilog list

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遥控器接收解码电路 Downloaded：6: Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit
Date : 2026-01-02 Size : 168kb User : yuguofang
dds1 Downloaded：0: DDS outputs a sine wave to control frequency by modifying the frequency control word
Date : 2026-01-02 Size : 5.31mb User : 明月惊心
PLX_SDK_v7_11_Final_2014-03-04 Downloaded：0: PLX Latest PCI Development Kit 2014-03-04 The latest version
Date : 2026-01-02 Size : 75.71mb User : leguldrdu
vivado_license_2016.4 Downloaded：0: vivado 2016.4 license
Date : 2026-01-02 Size : 1kb User : wowoqiang
dot_matrix Downloaded：0: The digital tube is from one to nine
Date : 2026-01-02 Size : 459kb User : nbca
spi_master Downloaded：0: Master slave mode of SPI communication
Date : 2026-01-02 Size : 4.97mb User : karviezz
code_cover_on_black_level_test_project1 Downloaded：0: The TB for the code coverage test of the video processing black level correction module
Date : 2026-01-02 Size : 89kb User : 莫勒
工作簿1 Downloaded：0: Just hole teacher talk, so that six new development of the party, you find a time, with the volunteer book, together to find the blue Secretary talk, @ Wang Kuo, you're responsible for this thing, a common time to go, go
Date : 2026-01-02 Size : 15kb User : 徐礼维
cpu_vhdl_vivado Downloaded：0: A basic CPU demo on the FPGA platform...
Date : 2026-01-02 Size : 1.2mb User : deadstar
oneMHZ Downloaded：0: 20Mhz frequency divider
Date : 2026-01-02 Size : 187kb User : zuys
spi_no_cs_13 Downloaded：0: Use FPGA as slave,realize the communication between FPGA and STM32. The function has been tested is no problem.
Date : 2026-01-02 Size : 13.74mb User : Pgaf
tx_rx_fifo Downloaded：0: Use fifo to realize the receive and send function of the uart. The function is no problem.
Date : 2026-01-02 Size : 3.62mb User : Pgaf

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