VHDL-FPGA-Verilog List Page 134

VHDL-FPGA-Verilog list

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tx_rx_fifo Downloaded：0: Use fifo to realize the receive and send function of the uart. The function is no problem.
Date : 2025-05-18 Size : 3.62mb User : Pgaf
ad706_test Downloaded：0: The drive program of AD7606 write by verilog. FPGA can convert the AD7606'sigal to volatage and send the converted signal to PC through uart.
Date : 2025-05-18 Size : 14.29mb User : Pgaf
OV7670_TFT Downloaded：0: OV7670 video capture and watermark function
Date : 2025-05-18 Size : 13.27mb User : rEAL_小明
VHDL2FSK Downloaded：0: The principle and code of each part of the VHDL 2FSK modem
Date : 2025-05-18 Size : 552kb User : 打发大叔大婶
rdf0028 Downloaded：1: Multiboot on Xilinx SP605
Date : 2025-05-18 Size : 906kb User : aguilarjp
rdf0029 Downloaded：0: DDR3 Memory Interface
Date : 2025-05-18 Size : 4.07mb User : aguilarjp
rdf0030 Downloaded：0: Restore Flash Contents
Date : 2025-05-18 Size : 6.95mb User : aguilarjp
rdf0031 Downloaded：0: MicroBlaze Built In Self Test
Date : 2025-05-18 Size : 1.05mb User : aguilarjp
rdf0032 Downloaded：0: Xilinx SP605 Built-In Self Test
Date : 2025-05-18 Size : 6.41mb User : aguilarjp
PWM Downloaded：0: The Verilog language is used to design a PWM controller, which is realized: the controller input clock 1MHz; the controller output pulse cycle 1kHz, and the pulse width minimum adjustment step 0.1%.
Date : 2025-05-18 Size : 61kb User : jcg17
pci9504 Downloaded：0: The Verilog language writes the interface circuit of the PCI9054 controller to realize the transfer control of the PCI bus to the local 8 bit bus
Date : 2025-05-18 Size : 20kb User : jcg17
vga_7_0728 Downloaded：0: With vga digital clock, through the serial port can control the time display
Date : 2025-05-18 Size : 12.32mb User : wuyezhiyue

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