VHDL-FPGA-Verilog List Page 1341

VHDL-FPGA-Verilog list

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AES_final_block_3 Downloaded：0: VHDL implementation of AES
Date : 2025-08-28 Size : 209kb User : mourya
design_1 Downloaded：0: Encoding latch is controlled by the host (start) and 6 the the players input (xuanshou (6:0)). Moderator signal is invalid (' 1 ' ), the intermediate variables Q_Z' 0' Fu ' 1 ' , the host signal (' 0
Date : 2025-08-28 Size : 58kb User : 张永满
design_2 Downloaded：0: Responder timer input is grab the signal, the clock signal and the host signal. When the host signal (' 0 ' ), the clock signal timing, grab began after the effective timing. First 48Mhz clock divider for a 1hz The
Date : 2025-08-28 Size : 59kb User : 张永满
design_3 Downloaded：0: Timer input is grab the signal and the clock signal. The clock signal timing, then grab effectively start timing. First 48Mhz clock divider for a 1hz The time signal, to grab the signal (' 0 ' ), the time to signal
Date : 2025-08-28 Size : 60kb User : 张永满
design_4 Downloaded：0: 48M clock signal timing delay set well in advance through the the delay signal received buzzer beep sound. Moderator, looting, to answer in time, answer time, four signals trigger count delay, the last three alarm signal
Date : 2025-08-28 Size : 60kb User : 张永满
design_5 Downloaded：0: 48M clock signal divider 1Khz signal by the output of the dig (2:0). Because the test board seven segment decoder monitors are common the same data line, must be provided to a fast scan signal (due to the stay of the hum
Date : 2025-08-28 Size : 55kb User : 张永满
video_stream_scaler Downloaded：0: The Video Stream Scaler (streamScaler) performs resizing of video streams in a low latency manner, resizing with either bilinear or nearest-neighbor modes.The core offers runtime configuration of input and output resolut
Date : 2025-08-28 Size : 11.21mb User : 高军
sdram_controller Downloaded：0: This application note describes the design of a FPGA SDRAM controller.The controller has a system interface on one side and a SDRAM controller for two 16 MB SDRAMs on the other side.It can be easily modified to fit diffe
Date : 2025-08-28 Size : 298kb User : 高军
ECE545_lecture9_FPGAs_6.pdf Downloaded：0: FPGA Lecture, from gmu.edu. Mostly based on Xilinx architectures but also partly on others.
Date : 2025-08-28 Size : 3.97mb User : Jomu
DAC0832 Downloaded：0: DAC0832 Verilog code, applicable at the same time with ADC0809 learning, the effect is obvious!
Date : 2025-08-28 Size : 22kb User : 杨开意
and_gate Downloaded：0: this is usefulland we can do it further also
Date : 2025-08-28 Size : 969kb User : brijesh
and3 Downloaded：0: The simulation example and3
Date : 2025-08-28 Size : 112kb User : beginner

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