VHDL-FPGA-Verilog List Page 1342

VHDL-FPGA-Verilog list

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D_flop Downloaded：0: D flip-flops used to set up the various timing logic circuit, is the most common trigger. VLSI are using the trigger.
Date : 2025-08-28 Size : 152kb User : 段开锋
fifo_syn Downloaded：0: Synchronous FIFO: it can complete data FIFO, when the FIFO full or empty time can you quote us full or empty signal.
Date : 2025-08-28 Size : 161kb User : 张明涛
odd_division Downloaded：0: Realize the clock odd (11) frequency divider, other odd frequency division as long as recount div1 and div2 parameters will do.
Date : 2025-08-28 Size : 30kb User : 张明涛
detector_Moore Downloaded：0: This procedure realize the series 101101 detection, whenever detection to the sequence is output 1, the Moore type state machine.
Date : 2025-08-28 Size : 66kb User : 张明涛
sale_newspaper Downloaded：0: The program has realized automatic sell newspaper machine, automatically change, input COINS have 1, 2, 5 points three, newspapers every 5 minutes.
Date : 2025-08-28 Size : 84kb User : 张明涛
Altera-FPGA-DE0 Downloaded：0: The Altera FPGA DE0 schematic contains the a classic FPGA design circuits and interface
Date : 2025-08-28 Size : 293kb User : rm
BlockRam Downloaded：0: xilinx FPGA BlockRam source.
Date : 2025-08-28 Size : 2kb User : zhanglingxiao
BramCfg Downloaded：0: xilinx FPGA BramCfg source.
Date : 2025-08-28 Size : 2kb User : zhanglingxiao
BramComCtrl Downloaded：0: xilinx FPGA BramComCtrl source.
Date : 2025-08-28 Size : 2kb User : zhanglingxiao
EppCtrlAsync Downloaded：0: xilinx FPGA EppCtrlAsync source.
Date : 2025-08-28 Size : 2kb User : zhanglingxiao
KIEMTRA3_1 Downloaded：0: Mo phong LEd sang chay vong vong
Date : 2025-08-28 Size : 80kb User : Ten Tui
Shift Downloaded：0: the this file a module shift a bit of 32 bits. it contains shift left and shift right. thank for visiting
Date : 2025-08-28 Size : 397kb User : tuan

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