VHDL-FPGA-Verilog List Page 1345

VHDL-FPGA-Verilog list

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cpld_ads7844_50M(9-24) Downloaded：0: Collected data using ads7844 timing control with cpld verilog prepared by the serial observe and record collection results through the development board verification
Date : 2025-08-28 Size : 642kb User : 王军
Countdown Downloaded：0: Digital clock EP2C5Q208C8. Digital display, regulation and control buttons.
Date : 2025-08-28 Size : 762kb User : anmko
digtal_clock Downloaded：0: C51 microcontroller, clock, alarm clock, time, prepared with Xilinx ISE Design
Date : 2025-08-28 Size : 772kb User : 刘阳
trafficlight Downloaded：0: Design topics: the design of the traffic lights at the crossroads. II. Design requirements: (a) assume that the system clock to 200Hz. (B) The design of the above requirements, the traffic lights, a countdown counter (tw
Date : 2025-08-28 Size : 971kb User : 董浩
fpga-for-ISE-and-Spartan Downloaded：0: Four counter with the Xilinx ISE9.2 and Spartan-3E
Date : 2025-08-28 Size : 313kb User : 武景
selfRst Downloaded：0: Used to generate a self-resetting signal, internal calibration, can ensure that no mistake is reset, the reset time can also be man-made.
Date : 2025-08-28 Size : 1kb User : 陈波
FPGA_IIC Downloaded：1: This is my own Verilog HDL program for IIC control, it can configure the EEPROM named 24C02, and the program have been tested.
Date : 2025-08-28 Size : 2kb User : 陈波
daojishi2 Downloaded：0: Board realized in the development of 5 seconds countdown, and in digital tube display digital
Date : 2025-08-28 Size : 361kb User : 李子
verilog Downloaded：0: the verilog code color sensors, curriculum design
Date : 2025-08-28 Size : 6.72mb User : 韦鹏
xiaobofilter Downloaded：0: Daubechies 4 filter group based on VHDL
Date : 2025-08-28 Size : 907kb User : 邱陈辉
cnt16 Downloaded：0: 16 counter VHDL implementation
Date : 2025-08-28 Size : 263kb User : 邱陈辉
jiou Downloaded：0: Design parity, VHDL programming, both odd parity Design, but also parity design
Date : 2025-08-28 Size : 236kb User : 邱陈辉

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