The Video Stream Scaler (streamScaler) performs resizing of video streams in a low latency manner, resizing with either bilinear or nearest-neighbor modes.The core offers runtime configuration of input and output resolution, scaling factors, and resize type. Data width, color channels and maximum video resolution can be configuredat compile time.

video_stream_scaler\doc\src\Block Diagram.vsd
...................\...\...\Video Stream Scaler Specifications.doc
...................\...\Video Stream Scaler Specifications.pdf
...................\rtl\verilog\scaler.v
...................\sim\rtl_sim\out\output1280x1024to480x384.raw
...................\...\.......\...\output1280x1024to640x512.raw
...................\...\.......\...\output1280x1024to960x768.raw
...................\...\.......\...\output50x40to640x512clipped.raw
...................\...\.......\...\output640x512to1280x1024.raw
...................\...\.......\...\output640x512to1280x1024_21extra.raw
...................\...\.......\...\output640x512to640x512.raw
...................\...\.......\scaler.cr.mti
...................\...\.......\scaler.mpf
...................\...\.......\scaler.v
...................\...\.......\scaler_tb.v
...................\...\.......\.rc\input.tif
...................\...\.......\...\input1280x1024boxdiag.bmp
...................\...\.......\...\input1280x1024boxdiagRGB.raw
...................\...\.......\...\input1280x1024RGB.raw
...................\...\.......\...\input640x512boxdiag.bmp
...................\...\.......\...\input640x512boxdiagRGB.raw
...................\...\.......\...\input640x512RGB.raw
...................\...\.......\...\input640x512_21extraRGB.raw
...................\...\.......\vsim.wlf
...................\...\.......\work\ram@dual@port\verilog.asm
...................\...\.......\....\.............\verilog.rw
...................\...\.......\....\.............\_primary.dat
...................\...\.......\....\.............\_primary.dbs
...................\...\.......\....\.............\_primary.vhd
...................\...\.......\....\....fifo\verilog.asm
...................\...\.......\....\........\verilog.rw
...................\...\.......\....\........\_primary.dat
...................\...\.......\....\........\_primary.dbs
...................\...\.......\....\........\_primary.vhd
...................\...\.......\....\scaler@test\verilog.asm
...................\...\.......\....\...........\verilog.rw
...................\...\.......\....\...........\_primary.dat
...................\...\.......\....\...........\_primary.dbs
...................\...\.......\....\...........\_primary.vhd
...................\...\.......\....\...........bench\verilog.asm
...................\...\.......\....\................\verilog.rw
...................\...\.......\....\................\_primary.dat
...................\...\.......\....\................\_primary.dbs
...................\...\.......\....\................\_primary.vhd
...................\...\.......\....\.tream@scaler\verilog.asm
...................\...\.......\....\.............\verilog.rw
...................\...\.......\....\.............\_primary.dat
...................\...\.......\....\.............\_primary.dbs
...................\...\.......\....\.............\_primary.vhd
...................\...\.......\....\_info
...................\...\.......\....\.temp\vlog3i6qcw
...................\...\.......\....\.....\vlog9xyg7b
...................\...\.......\....\.....\vlogg3009s
...................\...\.......\....\.....\vloggjv0st
...................\...\.......\....\_vmake
...................\...\.......\....\ram@dual@port
...................\...\.......\....\ram@fifo
...................\...\.......\....\scaler@test
...................\...\.......\....\scaler@testbench
...................\...\.......\....\stream@scaler
...................\...\.......\....\_temp
...................\...\.......\out
...................\...\.......\src
...................\...\.......\work
...................\doc\src
...................\rtl\verilog
...................\sim\rtl_sim
...................\doc
...................\rtl
...................\sim
video_stream_scaler

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