VHDL-FPGA-Verilog List Page 1187

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .82 .83 .84 .85 .86 1187.88 .89 .90 .91 .92 ... 4310 »

mult4x4 Downloaded：0: 4* 4 multiplier source code, FPGA lookup table to achieve classic digital circuit and FPGA multiplier source code
Date : 2025-08-22 Size : 43kb User : 冷先生
spi_iic Downloaded：0: spi_iic interface code, the use of lattice FPGA verification, the classic collection of circuit
Date : 2025-08-22 Size : 362kb User : 冷先生
driver8 Downloaded：0: Recent successful commissioning of the AD9928 initialization circuit connected to the CCD can be obtained by image, dedicated to you
Date : 2025-08-22 Size : 11.73mb User : 冷先生
MFSG Downloaded：0: To achieve a variable rate of the pseudo-random code generator. Mode selection via DIP switch, the mode selected by the digital display, and different modes correspond to different code rate pseudo-random code.
Date : 2025-08-22 Size : 3.25mb User : 余冰雁
CP_ADDER Downloaded：0: ISE development environment to achieve 802.11a physical layer OFDM system module of the cyclic prefix.
Date : 2025-08-22 Size : 2.2mb User : 余冰雁
DATA_16QAM_MAP Downloaded：0: ISE 802.11a physical layer OFDM constellation mapping module.
Date : 2025-08-22 Size : 380kb User : 余冰雁
cpld_now Downloaded：0: Multi-cycle synchronization method of frequency measurement procedures, crystal 40MHz measurement frequency between 15-30K, the output frequency of 100 Hz,
Date : 2025-08-22 Size : 472kb User : 石然
DATA_interleaver Downloaded：0: ISE development environment to achieve 802.11a physical layer OFDM system, interwoven module
Date : 2025-08-22 Size : 2.84mb User : 余冰雁
DATA_Pilot_Insert Downloaded：0: 802.11a physical layer OFDM system by inserting pilot module using ISE development environment to achieve
Date : 2025-08-22 Size : 2.42mb User : 余冰雁
IFFT Downloaded：0: ISE development environment inverse fft module 802.11a physical layer OFDM system
Date : 2025-08-22 Size : 8.72mb User : 余冰雁
uart_tx Downloaded：0: SP605 development board serial transmission program, and validation. Tested by serial debugging assistant!
Date : 2025-08-22 Size : 248kb User : 曹荣丽
clock Downloaded：0: This a eda design clock experiments, for your reference
Date : 2025-08-22 Size : 206kb User : ld

« 1 2 ... .82 .83 .84 .85 .86 1187.88 .89 .90 .91 .92 ... 4310 »

Search in result