VHDL-FPGA-Verilog List Page 1188

VHDL-FPGA-Verilog list

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uart-in-verilog Downloaded：0: develop uart using verilog language
Date : 2025-08-22 Size : 22kb User : Patel Dhaval P.
xds100v2-CPLD Downloaded：0: xds100v2 CPLD SOURCE xds100v2 CPLD SOURCE
Date : 2025-08-22 Size : 55kb User : zyc
xds100v2-lib Downloaded：0: xds100v2 lib xds100v2 库文件
Date : 2025-08-22 Size : 8kb User : zyc
ledscreen Downloaded：0: Lcd screen display program . Codeing in Verilog HDL .
Date : 2025-08-22 Size : 612kb User : 张宇嘉
2 Downloaded：0: (1) design a ' when' , ' points' , ' s' decimal digital display (hour timer from 00 to 23). (2) having a manual correction, the correction sub functions. (3) The alarm clock function, can send reminders
Date : 2025-08-22 Size : 2kb User : 张三
PCI_5Vjinshouzhi Downloaded：0: The definition and description of the PCI Universal Goldfinger, there are different Goldfinger instructions
Date : 2025-08-22 Size : 6kb User : zzy
-frequency_counter Downloaded：0: Contains the measured frequency meter, the key divider, seven segment LED display division factor and frequency of size, has been running on the development board, high precision, and contains the the modelsim simulation
Date : 2025-08-22 Size : 17.55mb User : jiazhaorong
washmachine Downloaded：0: An ordinary washing machine control circuit using VHDL language preparation, functional simulation, validation and development board using Altium Designer and NanBoard NB1, so that it can control the washing machine inle
Date : 2025-08-22 Size : 1.47mb User : 张水梅
sine-function-generator-by-VHDL Downloaded：0: 1, this experiment simulated sine function generator 2, the use of logic analyzer to check waveform 3,/proj/simulation directory in the modelsim simulation
Date : 2025-08-22 Size : 25.83mb User : 朱岩
fifo Downloaded：0: First-in, first-out first-i n, first-out first-i n, first-out
Date : 2025-08-22 Size : 1kb User : dd
verilog_LCD12864 Downloaded：0: LCD12864 display Chinese characters verilog language
Date : 2025-08-22 Size : 407kb User : 王先生
add_tree Downloaded：0: Adder tree source code, multiplication and division, digital circuit verilog code base simulation entirely correct
Date : 2025-08-22 Size : 39kb User : 冷先生

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