VHDL-FPGA-Verilog List Page 1079

VHDL-FPGA-Verilog list

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hitmouse Downloaded：0: FPGA-based fighting to control the experiment source code. Can be extended for a similar program to play the piano.
Date : 2025-08-16 Size : 6.73mb User : 彭元杰
eda_shiyanbaogao Downloaded：0: eda lab reports, including full-adder, four elected a data selector, traffic lights.
Date : 2025-08-16 Size : 68kb User : 安琪
verilog-uart-rs232 Downloaded：0: verilog HDL description uart program Received by the PC side and then+1 back。 SEU
Date : 2025-08-16 Size : 575kb User : yu
CPU Downloaded：0: Southeast University, CPU design Verilog language VHDL course
Date : 2025-08-16 Size : 506kb User : yu
lab2_cordic Downloaded：0: Implemented on FPGA Cordic algorithm is used to compute sin (x). Cordic algorithm stands Coordinate Rotation Digital Computer, can be used to achieve a variety of transcendental function arithmetic.
Date : 2025-08-16 Size : 3kb User : 金继仁
1 Downloaded：0: Use VHDL cymometer design validation
Date : 2025-08-16 Size : 12kb User : xuebing
state_machine Downloaded：0: verilog programming state machine combat training: 1. This example by implementing a state machine to control 8 LED flashing cycle 2 works in the project folder inside 3 pin assignments in the source file and folder insi
Date : 2025-08-16 Size : 809kb User : 李海军
Odd-Frequence-Dividing-Circuit Downloaded：0: A design of odd frequence dividing circuit is presented, which is described by verilog HDL。Change the parameter in code, one can get any odd numbers of frequence dividing circuit.
Date : 2025-08-16 Size : 94kb User : zhouwen
add4_fast_carry Downloaded：0: This a carry lookahead adder design, which is simulated successfully in modelsim.
Date : 2025-08-16 Size : 69kb User : zhouwen
FSM_3blocks Downloaded：0: A classical FSM of three paragrahs, which is described by verilog HDL and simulated in modelsim successfully.
Date : 2025-08-16 Size : 61kb User : zhouwen
ic2 Downloaded：0: This a IC2 design, which is simulated successfully in modelsim.
Date : 2025-08-16 Size : 115kb User : zhouwen
cordic_pipelined Downloaded：0: This an implementation of CORDIC algorithm in verilog HDL, which contains design code and testbench.
Date : 2025-08-16 Size : 1kb User : zhouwen

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