VHDL-FPGA-Verilog List Page 1083

VHDL-FPGA-Verilog list

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hsk4571_clock Downloaded：0: Digital clock VHDL realization, minutes and seconds can be adjusted in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for Altera' s Cyclone3 EP3C8T1
Date : 2025-08-17 Size : 4.87mb User : hongsk
hsk4571_cuankou Downloaded：0: Serial communication SCI VHDL realize, in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for Altera' s Cyclone3 EP3C8T1
Date : 2025-08-17 Size : 42kb User : hongsk
hsk4571_sgna_generator Downloaded：0: Signal Generator VHDL implementation, adjustable waveform and frequency, square wave, sawtooth, triangle, etc., in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for Alter
Date : 2025-08-17 Size : 9.28mb User : hongsk
VHDL Downloaded：0: Digital circuit experiment program code package download version Ningbo University academic year programming section VHDl digital circuit experiment
Date : 2025-08-17 Size : 2.31mb User : mengchenyezi
FPGA- Downloaded：0: FPGA Implementation of serial interface RS232, RS232, including how it works, how to produce the desired baud rate, transmit module, receiver module, application examples
Date : 2025-08-17 Size : 218kb User : 陈静
fpga_nes-master Downloaded：0: This a complete NES nes games fpga implementation, the test is available, use ise14.1 above version of the project file, the development board using xilinx spartan6
Date : 2025-08-17 Size : 19.49mb User : 于洋
NOIS-II_AES Downloaded：0: NOIS II-based AES encryption and decryption of a complete project file system
Date : 2025-08-17 Size : 6.42mb User : 于洋
project2_1 Downloaded：0: 3:8 decoder, HDl verilog language, able to run on the DE2
Date : 2025-08-17 Size : 239kb User : 董凯明
project2_2 Downloaded：0: 7 segment decoder tube used to display numbers, HDl verilog language, can be run on the DE2
Date : 2025-08-17 Size : 261kb User : 董凯明
project3_1 Downloaded：0: Successive carry adder, HDl verilog language, able to run on the DE2
Date : 2025-08-17 Size : 263kb User : 董凯明
project4_1 Downloaded：0: D flip-flop gate-level implementation, there are asynchronous Reset_Set, HDl verilog language, able to run on the DE2
Date : 2025-08-17 Size : 238kb User : 董凯明
go-to-the-digital-world-of-FPGA Downloaded：0: FPGA into the digital world, so that we are more easy to understand to understand FPGA, to understand numbers.
Date : 2025-08-17 Size : 2.82mb User : lin

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